cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell-neta-bm.txt (1509B)


      1* Marvell Armada 380/XP Buffer Manager driver (BM)
      2
      3Required properties:
      4
      5- compatible: should be "marvell,armada-380-neta-bm".
      6- reg: address and length of the register set for the device.
      7- clocks: a pointer to the reference clock for this device.
      8- internal-mem: a phandle to BM internal SRAM definition.
      9
     10Optional properties (port):
     11
     12- pool<0 : 3>,capacity: size of external buffer pointers' ring maintained
     13  in DRAM. Can be set for each pool (id 0 : 3) separately. The value has
     14  to be chosen between 128 and 16352 and it also has to be aligned to 32.
     15  Otherwise the driver would adjust a given number or choose default if
     16  not set.
     17- pool<0 : 3>,pkt-size: maximum size of a packet accepted by a given buffer
     18  pointers' pool (id 0 : 3). It will be taken into consideration only when pool
     19  type is 'short'. For 'long' ones it would be overridden by port's MTU.
     20  If not set a driver will choose a default value.
     21
     22In order to see how to hook the BM to a given ethernet port, please
     23refer to Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt.
     24
     25Example:
     26
     27- main node:
     28
     29bm: bm@c8000 {
     30	compatible = "marvell,armada-380-neta-bm";
     31	reg = <0xc8000 0xac>;
     32	clocks = <&gateclk 13>;
     33	internal-mem = <&bm_bppi>;
     34	pool2,capacity = <4096>;
     35	pool1,pkt-size = <512>;
     36};
     37
     38- internal SRAM node:
     39
     40bm_bppi: bm-bppi {
     41	compatible = "mmio-sram";
     42	reg = <MBUS_ID(0x0c, 0x04) 0 0x100000>;
     43	ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x100000>;
     44	#address-cells = <1>;
     45	#size-cells = <1>;
     46	clocks = <&gateclk 13>;
     47};