cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell-pxa168.txt (1038B)

      1* Marvell PXA168 Ethernet Controller
      2
      3Required properties:
      4- compatible: should be "marvell,pxa168-eth".
      5- reg: address and length of the register set for the device.
      6- interrupts: interrupt for the device.
      7- clocks: pointer to the clock for the device.
      8
      9Optional properties:
     10- port-id: Ethernet port number. Should be '0','1' or '2'.
     11- #address-cells: must be 1 when using sub-nodes.
     12- #size-cells: must be 0 when using sub-nodes.
     13- phy-handle: see ethernet.txt file in the same directory.
     14
     15The MAC address will be determined using the optional properties
     16defined in ethernet.txt.
     17
     18Sub-nodes:
     19Each PHY can be represented as a sub-node. This is not mandatory.
     20
     21Sub-nodes required properties:
     22- reg: the MDIO address of the PHY.
     23
     24Example:
     25
     26	eth0: ethernet@f7b90000 {
     27		compatible = "marvell,pxa168-eth";
     28		reg = <0xf7b90000 0x10000>;
     29		clocks = <&chip CLKID_GETH0>;
     30		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
     31		#address-cells = <1>;
     32		#size-cells = <0>;
     33		phy-handle = <&ethphy0>;
     34
     35		ethphy0: ethernet-phy@0 {
     36			reg = <0>;
     37		};
     38	};