cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mdio-mux-meson-g12a.txt (1298B)


      1Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
      2
      3This is a special case of a MDIO bus multiplexer. It allows to choose between
      4the internal mdio bus leading to the embedded 10/100 PHY or the external
      5MDIO bus.
      6
      7Required properties in addition to the generic multiplexer properties:
      8- compatible : amlogic,g12a-mdio-mux
      9- reg: physical address and length of the multiplexer/glue registers
     10- clocks: list of clock phandle, one for each entry clock-names.
     11- clock-names: should contain the following:
     12  * "pclk"   : peripheral clock.
     13  * "clkin0" : platform crytal
     14  * "clkin1" : SoC 50MHz MPLL
     15
     16Example :
     17
     18mdio_mux: mdio-multiplexer@4c000 {
     19	compatible = "amlogic,g12a-mdio-mux";
     20	reg = <0x0 0x4c000 0x0 0xa4>;
     21	clocks = <&clkc CLKID_ETH_PHY>,
     22		 <&xtal>,
     23		 <&clkc CLKID_MPLL_5OM>;
     24	clock-names = "pclk", "clkin0", "clkin1";
     25	mdio-parent-bus = <&mdio0>;
     26	#address-cells = <1>;
     27	#size-cells = <0>;
     28
     29	ext_mdio: mdio@0 {
     30		reg = <0>;
     31		#address-cells = <1>;
     32		#size-cells = <0>;
     33	};
     34
     35	int_mdio: mdio@1 {
     36		reg = <1>;
     37		#address-cells = <1>;
     38		#size-cells = <0>;
     39
     40		internal_ephy: ethernet-phy@8 {
     41			compatible = "ethernet-phy-id0180.3301",
     42				     "ethernet-phy-ieee802.3-c22";
     43			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
     44			reg = <8>;
     45			max-speed = <100>;
     46		};
     47	};
     48};