cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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microchip,enc28j60.txt (2340B)

      1* Microchip ENC28J60
      2
      3This is a standalone 10 MBit ethernet controller with SPI interface.
      4
      5For each device connected to a SPI bus, define a child node within
      6the SPI master node.
      7
      8Required properties:
      9- compatible: Should be "microchip,enc28j60"
     10- reg: Specify the SPI chip select the ENC28J60 is wired to
     11- interrupts: Specify the interrupt index within the interrupt controller (referred
     12              to above in interrupt-parent) and interrupt type. The ENC28J60 natively
     13              generates falling edge interrupts, however, additional board logic
     14              might invert the signal.
     15- pinctrl-names: List of assigned state names, see pinctrl binding documentation.
     16- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
     17             see also generic and your platform specific pinctrl binding
     18             documentation.
     19
     20Optional properties:
     21- spi-max-frequency: Maximum frequency of the SPI bus when accessing the ENC28J60.
     22  According to the ENC28J80 datasheet, the chip allows a maximum of 20 MHz, however,
     23  board designs may need to limit this value.
     24
     25The MAC address will be determined using the optional properties
     26defined in ethernet.txt.
     27
     28Example (for NXP i.MX28 with pin control stuff for GPIO irq):
     29
     30        ssp2: ssp@80014000 {
     31                compatible = "fsl,imx28-spi";
     32                pinctrl-names = "default";
     33                pinctrl-0 = <&spi2_pins_b &spi2_sck_cfg>;
     34
     35                enc28j60: ethernet@0 {
     36                        compatible = "microchip,enc28j60";
     37                        pinctrl-names = "default";
     38                        pinctrl-0 = <&enc28j60_pins>;
     39                        reg = <0>;
     40                        interrupt-parent = <&gpio3>;
     41                        interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
     42                        spi-max-frequency = <12000000>;
     43                };
     44        };
     45
     46        pinctrl@80018000 {
     47                enc28j60_pins: enc28j60_pins@0 {
     48                        reg = <0>;
     49                        fsl,pinmux-ids = <
     50                                MX28_PAD_AUART0_RTS__GPIO_3_3    /* Interrupt */
     51                        >;
     52                        fsl,drive-strength = <MXS_DRIVE_4mA>;
     53                        fsl,voltage = <MXS_VOLTAGE_HIGH>;
     54                        fsl,pull-up = <MXS_PULL_DISABLE>;
     55                };
     56        };