cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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microchip,lan966x-switch.yaml (3714B)


      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Microchip Lan966x Ethernet switch controller
      8
      9maintainers:
     10  - Horatiu Vultur <horatiu.vultur@microchip.com>
     11
     12description: |
     13  The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
     14  two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
     15  it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
     16  2 Quad-SGMII/Quad-USGMII interfaces.
     17
     18properties:
     19  $nodename:
     20    pattern: "^switch@[0-9a-f]+$"
     21
     22  compatible:
     23    const: microchip,lan966x-switch
     24
     25  reg:
     26    items:
     27      - description: cpu target
     28      - description: general control block target
     29
     30  reg-names:
     31    items:
     32      - const: cpu
     33      - const: gcb
     34
     35  interrupts:
     36    minItems: 1
     37    items:
     38      - description: register based extraction
     39      - description: frame dma based extraction
     40      - description: analyzer interrupt
     41      - description: ptp interrupt
     42      - description: ptp external interrupt
     43
     44  interrupt-names:
     45    minItems: 1
     46    items:
     47      - const: xtr
     48      - const: fdma
     49      - const: ana
     50      - const: ptp
     51      - const: ptp-ext
     52
     53  resets:
     54    items:
     55      - description: Reset controller used for switch core reset (soft reset)
     56
     57  reset-names:
     58    items:
     59      - const: switch
     60
     61  ethernet-ports:
     62    type: object
     63
     64    properties:
     65      '#address-cells':
     66        const: 1
     67      '#size-cells':
     68        const: 0
     69
     70    additionalProperties: false
     71
     72    patternProperties:
     73      "^port@[0-9a-f]+$":
     74        type: object
     75
     76        $ref: "/schemas/net/ethernet-controller.yaml#"
     77        unevaluatedProperties: false
     78
     79        properties:
     80          '#address-cells':
     81            const: 1
     82          '#size-cells':
     83            const: 0
     84
     85          reg:
     86            description:
     87              Switch port number
     88
     89          phys:
     90            description:
     91              Phandle of a Ethernet SerDes PHY
     92
     93          phy-mode:
     94            description:
     95              This specifies the interface used by the Ethernet SerDes towards
     96              the PHY or SFP.
     97            enum:
     98              - gmii
     99              - sgmii
    100              - qsgmii
    101              - 1000base-x
    102              - 2500base-x
    103
    104          phy-handle:
    105            description:
    106              Phandle of a Ethernet PHY.
    107
    108          sfp:
    109            description:
    110              Phandle of an SFP.
    111
    112          managed: true
    113
    114        required:
    115          - reg
    116          - phys
    117          - phy-mode
    118
    119        oneOf:
    120          - required:
    121              - phy-handle
    122          - required:
    123              - sfp
    124              - managed
    125
    126required:
    127  - compatible
    128  - reg
    129  - reg-names
    130  - interrupts
    131  - interrupt-names
    132  - resets
    133  - reset-names
    134  - ethernet-ports
    135
    136additionalProperties: false
    137
    138examples:
    139  - |
    140    #include <dt-bindings/interrupt-controller/arm-gic.h>
    141    switch: switch@e0000000 {
    142      compatible = "microchip,lan966x-switch";
    143      reg =  <0xe0000000 0x0100000>,
    144             <0xe2000000 0x0800000>;
    145      reg-names = "cpu", "gcb";
    146      interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
    147      interrupt-names = "xtr";
    148      resets = <&switch_reset 0>;
    149      reset-names = "switch";
    150      ethernet-ports {
    151        #address-cells = <1>;
    152        #size-cells = <0>;
    153
    154        port0: port@0 {
    155          reg = <0>;
    156          phy-handle = <&phy0>;
    157          phys = <&serdes 0 0>;
    158          phy-mode = "gmii";
    159        };
    160
    161        port1: port@1 {
    162          reg = <1>;
    163          sfp = <&sfp_eth1>;
    164          managed = "in-band-status";
    165          phys = <&serdes 2 4>;
    166          phy-mode = "sgmii";
    167        };
    168      };
    169    };
    170
    171...