microchip,sparx5-switch.yaml (6221B)
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/net/microchip,sparx5-switch.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Microchip Sparx5 Ethernet switch controller 8 9maintainers: 10 - Steen Hegelund <steen.hegelund@microchip.com> 11 - Lars Povlsen <lars.povlsen@microchip.com> 12 13description: | 14 The SparX-5 Enterprise Ethernet switch family provides a rich set of 15 Enterprise switching features such as advanced TCAM-based VLAN and 16 QoS processing enabling delivery of differentiated services, and 17 security through TCAM-based frame processing using versatile content 18 aware processor (VCAP). 19 20 IPv4/IPv6 Layer 3 (L3) unicast and multicast routing is supported 21 with up to 18K IPv4/9K IPv6 unicast LPM entries and up to 9K IPv4/3K 22 IPv6 (S,G) multicast groups. 23 24 L3 security features include source guard and reverse path 25 forwarding (uRPF) tasks. Additional L3 features include VRF-Lite and 26 IP tunnels (IP over GRE/IP). 27 28 The SparX-5 switch family targets managed Layer 2 and Layer 3 29 equipment in SMB, SME, and Enterprise where high port count 30 1G/2.5G/5G/10G switching with 10G/25G aggregation links is required. 31 32properties: 33 $nodename: 34 pattern: "^switch@[0-9a-f]+$" 35 36 compatible: 37 const: microchip,sparx5-switch 38 39 reg: 40 items: 41 - description: cpu target 42 - description: devices target 43 - description: general control block target 44 45 reg-names: 46 items: 47 - const: cpu 48 - const: devices 49 - const: gcb 50 51 interrupts: 52 minItems: 1 53 items: 54 - description: register based extraction 55 - description: frame dma based extraction 56 - description: ptp interrupt 57 58 interrupt-names: 59 minItems: 1 60 items: 61 - const: xtr 62 - const: fdma 63 - const: ptp 64 65 resets: 66 items: 67 - description: Reset controller used for switch core reset (soft reset) 68 69 reset-names: 70 items: 71 - const: switch 72 73 mac-address: true 74 75 ethernet-ports: 76 type: object 77 patternProperties: 78 "^port@[0-9a-f]+$": 79 type: object 80 81 properties: 82 '#address-cells': 83 const: 1 84 '#size-cells': 85 const: 0 86 87 reg: 88 description: Switch port number 89 90 phys: 91 maxItems: 1 92 description: 93 phandle of a Ethernet SerDes PHY. This defines which SerDes 94 instance will handle the Ethernet traffic. 95 96 phy-mode: 97 description: 98 This specifies the interface used by the Ethernet SerDes towards 99 the PHY or SFP. 100 101 microchip,bandwidth: 102 description: Specifies bandwidth in Mbit/s allocated to the port. 103 $ref: "/schemas/types.yaml#/definitions/uint32" 104 maximum: 25000 105 106 phy-handle: 107 description: 108 phandle of a Ethernet PHY. This is optional and if provided it 109 points to the cuPHY used by the Ethernet SerDes. 110 111 sfp: 112 description: 113 phandle of an SFP. This is optional and used when not specifying 114 a cuPHY. It points to the SFP node that describes the SFP used by 115 the Ethernet SerDes. 116 117 managed: true 118 119 microchip,sd-sgpio: 120 description: 121 Index of the ports Signal Detect SGPIO in the set of 384 SGPIOs 122 This is optional, and only needed if the default used index is 123 is not correct. 124 $ref: "/schemas/types.yaml#/definitions/uint32" 125 minimum: 0 126 maximum: 383 127 128 required: 129 - reg 130 - phys 131 - phy-mode 132 - microchip,bandwidth 133 134 oneOf: 135 - required: 136 - phy-handle 137 - required: 138 - sfp 139 - managed 140 141required: 142 - compatible 143 - reg 144 - reg-names 145 - interrupts 146 - interrupt-names 147 - resets 148 - reset-names 149 - ethernet-ports 150 151additionalProperties: false 152 153examples: 154 - | 155 #include <dt-bindings/interrupt-controller/arm-gic.h> 156 switch: switch@600000000 { 157 compatible = "microchip,sparx5-switch"; 158 reg = <0 0x401000>, 159 <0x10004000 0x7fc000>, 160 <0x11010000 0xaf0000>; 161 reg-names = "cpu", "devices", "gcb"; 162 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 163 interrupt-names = "xtr"; 164 resets = <&reset 0>; 165 reset-names = "switch"; 166 ethernet-ports { 167 #address-cells = <1>; 168 #size-cells = <0>; 169 170 port0: port@0 { 171 reg = <0>; 172 microchip,bandwidth = <1000>; 173 phys = <&serdes 13>; 174 phy-handle = <&phy0>; 175 phy-mode = "qsgmii"; 176 }; 177 /* ... */ 178 /* Then the 25G interfaces */ 179 port60: port@60 { 180 reg = <60>; 181 microchip,bandwidth = <25000>; 182 phys = <&serdes 29>; 183 phy-mode = "10gbase-r"; 184 sfp = <&sfp_eth60>; 185 managed = "in-band-status"; 186 microchip,sd-sgpio = <365>; 187 }; 188 port61: port@61 { 189 reg = <61>; 190 microchip,bandwidth = <25000>; 191 phys = <&serdes 30>; 192 phy-mode = "10gbase-r"; 193 sfp = <&sfp_eth61>; 194 managed = "in-band-status"; 195 microchip,sd-sgpio = <369>; 196 }; 197 port62: port@62 { 198 reg = <62>; 199 microchip,bandwidth = <25000>; 200 phys = <&serdes 31>; 201 phy-mode = "10gbase-r"; 202 sfp = <&sfp_eth62>; 203 managed = "in-band-status"; 204 microchip,sd-sgpio = <373>; 205 }; 206 port63: port@63 { 207 reg = <63>; 208 microchip,bandwidth = <25000>; 209 phys = <&serdes 32>; 210 phy-mode = "10gbase-r"; 211 sfp = <&sfp_eth63>; 212 managed = "in-band-status"; 213 microchip,sd-sgpio = <377>; 214 }; 215 /* Finally the Management interface */ 216 port64: port@64 { 217 reg = <64>; 218 microchip,bandwidth = <1000>; 219 phys = <&serdes 0>; 220 phy-handle = <&phy64>; 221 phy-mode = "sgmii"; 222 mac-address = [ 00 00 00 01 02 03 ]; 223 }; 224 }; 225 }; 226 227... 228# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml :