cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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mscc,miim.yaml (1073B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/net/mscc,miim.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Microsemi MII Management Controller (MIIM)
      8
      9maintainers:
     10  - Alexandre Belloni <alexandre.belloni@bootlin.com>
     11
     12allOf:
     13  - $ref: "mdio.yaml#"
     14
     15properties:
     16  compatible:
     17    enum:
     18      - mscc,ocelot-miim
     19      - microchip,lan966x-miim
     20
     21  "#address-cells":
     22    const: 1
     23
     24  "#size-cells":
     25    const: 0
     26
     27  reg:
     28    items:
     29      - description: base address
     30      - description: associated reset register for internal PHYs
     31    minItems: 1
     32
     33  interrupts:
     34    maxItems: 1
     35
     36  clocks:
     37    maxItems: 1
     38
     39  clock-frequency: true
     40
     41required:
     42  - compatible
     43  - reg
     44  - "#address-cells"
     45  - "#size-cells"
     46
     47unevaluatedProperties: false
     48
     49examples:
     50  - |
     51    mdio@107009c {
     52      compatible = "mscc,ocelot-miim";
     53      reg = <0x107009c 0x36>, <0x10700f0 0x8>;
     54      interrupts = <14>;
     55      #address-cells = <1>;
     56      #size-cells = <0>;
     57
     58      phy0: ethernet-phy@0 {
     59        reg = <0>;
     60      };
     61    };