cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,nci.yaml (3581B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/net/nfc/marvell,nci.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Marvell International Ltd. NCI NFC controller
      8
      9maintainers:
     10  - Krzysztof Kozlowski <krzk@kernel.org>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - marvell,nfc-i2c
     16      - marvell,nfc-spi
     17      - marvell,nfc-uart
     18
     19  hci-muxed:
     20    type: boolean
     21    description: |
     22      Specifies that the chip is muxing NCI over HCI frames
     23
     24  interrupts:
     25    maxItems: 1
     26
     27  reg:
     28    maxItems: 1
     29
     30  reset-n-io:
     31    $ref: "/schemas/types.yaml#/definitions/phandle-array"
     32    maxItems: 1
     33    description: |
     34      Output GPIO pin used to reset the chip (active low)
     35
     36  i2c-int-falling:
     37    type: boolean
     38    description: |
     39      For I2C type of connection. Specifies that the chip read event shall be
     40      trigged on falling edge.
     41
     42  i2c-int-rising:
     43    type: boolean
     44    description: |
     45      For I2C type of connection.  Specifies that the chip read event shall be
     46      trigged on rising edge.
     47
     48  break-control:
     49    type: boolean
     50    description: |
     51      For UART type of connection. Specifies that the chip needs specific break
     52      management.
     53
     54  flow-control:
     55    type: boolean
     56    description: |
     57      For UART type of connection. Specifies that the chip is using RTS/CTS.
     58
     59  spi-cpha: true
     60  spi-cpol: true
     61  spi-max-frequency: true
     62
     63required:
     64  - compatible
     65
     66allOf:
     67  - if:
     68      properties:
     69        compatible:
     70          contains:
     71            const: marvell,nfc-i2c
     72    then:
     73      properties:
     74        break-control: false
     75        flow-control: false
     76        spi-cpha: false
     77        spi-cpol: false
     78        spi-max-frequency: false
     79      required:
     80        - reg
     81
     82  - if:
     83      properties:
     84        compatible:
     85          contains:
     86            const: marvell,nfc-spi
     87    then:
     88      properties:
     89        break-control: false
     90        flow-control: false
     91        i2c-int-falling: false
     92        i2c-int-rising: false
     93      required:
     94        - reg
     95
     96  - if:
     97      properties:
     98        compatible:
     99          contains:
    100            const: marvell,nfc-uart
    101    then:
    102      properties:
    103        i2c-int-falling: false
    104        i2c-int-rising: false
    105        interrupts: false
    106        spi-cpha: false
    107        spi-cpol: false
    108        spi-max-frequency: false
    109        reg: false
    110
    111additionalProperties: false
    112
    113examples:
    114  - |
    115    #include <dt-bindings/gpio/gpio.h>
    116    #include <dt-bindings/interrupt-controller/irq.h>
    117
    118    i2c {
    119        #address-cells = <1>;
    120        #size-cells = <0>;
    121
    122        nfc@8 {
    123            compatible = "marvell,nfc-i2c";
    124            reg = <0x8>;
    125
    126            interrupt-parent = <&gpio3>;
    127            interrupts = <21 IRQ_TYPE_EDGE_RISING>;
    128
    129            i2c-int-rising;
    130
    131            reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>;
    132        };
    133    };
    134
    135  - |
    136    #include <dt-bindings/gpio/gpio.h>
    137    #include <dt-bindings/interrupt-controller/irq.h>
    138
    139    spi {
    140        #address-cells = <1>;
    141        #size-cells = <0>;
    142
    143        nfc@0 {
    144            compatible = "marvell,nfc-spi";
    145            reg = <0>;
    146
    147            spi-max-frequency = <3000000>;
    148            spi-cpha;
    149            spi-cpol;
    150
    151            interrupt-parent = <&gpio1>;
    152            interrupts = <17 IRQ_TYPE_EDGE_RISING>;
    153
    154            reset-n-io = <&gpio3 19 GPIO_ACTIVE_HIGH>;
    155        };
    156    };
    157
    158  - |
    159    #include <dt-bindings/gpio/gpio.h>
    160
    161    uart {
    162        nfc {
    163            compatible = "marvell,nfc-uart";
    164
    165            reset-n-io = <&gpio3 16 GPIO_ACTIVE_HIGH>;
    166
    167            hci-muxed;
    168            flow-control;
    169        };
    170    };