cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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st,st-nci.yaml (2137B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/net/nfc/st,st-nci.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: STMicroelectronics ST NCI NFC controller
      8
      9maintainers:
     10  - Krzysztof Kozlowski <krzk@kernel.org>
     11
     12properties:
     13  compatible:
     14    enum:
     15      - st,st21nfcb-i2c
     16      - st,st21nfcb-spi
     17      - st,st21nfcc-i2c
     18
     19  reset-gpios:
     20    description: Output GPIO pin used for resetting the controller
     21
     22  ese-present:
     23    type: boolean
     24    description: |
     25      Specifies that an ese is physically connected to the controller
     26
     27  interrupts:
     28    maxItems: 1
     29
     30  reg:
     31    maxItems: 1
     32
     33  spi-max-frequency: true
     34
     35  uicc-present:
     36    type: boolean
     37    description: |
     38      Specifies that the uicc swp signal can be physically connected to the
     39      controller
     40
     41required:
     42  - compatible
     43  - interrupts
     44  - reg
     45  - reset-gpios
     46
     47if:
     48  properties:
     49    compatible:
     50      contains:
     51        enum:
     52          - st,st21nfcb-i2c
     53          - st,st21nfcc-i2c
     54then:
     55  properties:
     56    spi-max-frequency: false
     57else:
     58  required:
     59    - spi-max-frequency
     60
     61additionalProperties: false
     62
     63examples:
     64  - |
     65    #include <dt-bindings/gpio/gpio.h>
     66    #include <dt-bindings/interrupt-controller/irq.h>
     67
     68    i2c {
     69        #address-cells = <1>;
     70        #size-cells = <0>;
     71
     72        nfc@8 {
     73            compatible = "st,st21nfcb-i2c";
     74            reg = <0x08>;
     75
     76            interrupt-parent = <&gpio5>;
     77            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
     78            reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
     79
     80            ese-present;
     81            uicc-present;
     82        };
     83    };
     84
     85  - |
     86    #include <dt-bindings/gpio/gpio.h>
     87    #include <dt-bindings/interrupt-controller/irq.h>
     88
     89    spi {
     90        #address-cells = <1>;
     91        #size-cells = <0>;
     92
     93        nfc@0 {
     94            compatible = "st,st21nfcb-spi";
     95            reg = <0>;
     96
     97            spi-max-frequency = <4000000>;
     98
     99            interrupt-parent = <&gpio5>;
    100            interrupts = <2 IRQ_TYPE_EDGE_RISING>;
    101            reset-gpios = <&gpio5 29 GPIO_ACTIVE_HIGH>;
    102
    103            ese-present;
    104            uicc-present;
    105        };
    106    };