cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nixge.txt (2586B)

      1* NI XGE Ethernet controller
      2
      3Required properties:
      4- compatible: Should be "ni,xge-enet-3.00", but can be "ni,xge-enet-2.00" for
      5              older device trees with DMA engines co-located in the address map,
      6              with the one reg entry to describe the whole device.
      7- reg: Address and length of the register set for the device. It contains the
      8       information of registers in the same order as described by reg-names.
      9- reg-names: Should contain the reg names
     10	"dma":  DMA engine control and status region
     11        "ctrl": MDIO and PHY control and status region
     12- interrupts: Should contain tx and rx interrupt
     13- interrupt-names: Should be "rx" and "tx"
     14- phy-mode: See ethernet.txt file in the same directory.
     15- nvmem-cells: Phandle of nvmem cell containing the MAC address
     16- nvmem-cell-names: Should be "address"
     17
     18Optional properties:
     19- mdio subnode to indicate presence of MDIO controller
     20- fixed-link : Assume a fixed link. See fixed-link.txt in the same directory.
     21  Use instead of phy-handle.
     22- phy-handle: See ethernet.txt file in the same directory.
     23
     24Examples (10G generic PHY):
     25	nixge0: ethernet@40000000 {
     26		compatible = "ni,xge-enet-3.00";
     27		reg = <0x40000000 0x4000
     28		       0x41002000 0x2000>;
     29		reg-names = "dma", "ctrl";
     30
     31		nvmem-cells = <&eth1_addr>;
     32		nvmem-cell-names = "address";
     33
     34		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
     35		interrupt-names = "rx", "tx";
     36		interrupt-parent = <&intc>;
     37
     38		phy-mode = "xgmii";
     39		phy-handle = <&ethernet_phy1>;
     40
     41		mdio {
     42			ethernet_phy1: ethernet-phy@4 {
     43				compatible = "ethernet-phy-ieee802.3-c45";
     44				reg = <4>;
     45			};
     46		};
     47	};
     48
     49Examples (10G generic PHY, no MDIO):
     50	nixge0: ethernet@40000000 {
     51		compatible = "ni,xge-enet-2.00";
     52		reg = <0x40000000 0x6000>;
     53
     54		nvmem-cells = <&eth1_addr>;
     55		nvmem-cell-names = "address";
     56
     57		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
     58		interrupt-names = "rx", "tx";
     59		interrupt-parent = <&intc>;
     60
     61		phy-mode = "xgmii";
     62		phy-handle = <&ethernet_phy1>;
     63	};
     64
     65Examples (1G generic fixed-link + MDIO):
     66	nixge0: ethernet@40000000 {
     67		compatible = "ni,xge-enet-2.00";
     68		reg = <0x40000000 0x6000>;
     69
     70		nvmem-cells = <&eth1_addr>;
     71		nvmem-cell-names = "address";
     72
     73		interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>, <0 30 IRQ_TYPE_LEVEL_HIGH>;
     74		interrupt-names = "rx", "tx";
     75		interrupt-parent = <&intc>;
     76
     77		phy-mode = "xgmii";
     78
     79		fixed-link {
     80			speed = <1000>;
     81			pause;
     82			link-gpios = <&gpio0 63 GPIO_ACTIVE_HIGH>;
     83		};
     84
     85		mdio {
     86			ethernet_phy1: ethernet-phy@4 {
     87				compatible = "ethernet-phy-ieee802.3-c22";
     88				reg = <4>;
     89			};
     90		};
     91
     92	};