cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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oxnas-dwmac.txt (1281B)


      1* Oxford Semiconductor OXNAS DWMAC Ethernet controller
      2
      3The device inherits all the properties of the dwmac/stmmac devices
      4described in the file stmmac.txt in the current directory with the
      5following changes.
      6
      7Required properties on all platforms:
      8
      9- compatible:	For the OX820 SoC, it should be :
     10		- "oxsemi,ox820-dwmac" to select glue
     11		- "snps,dwmac-3.512" to select IP version.
     12		For the OX810SE SoC, it should be :
     13		- "oxsemi,ox810se-dwmac" to select glue
     14		- "snps,dwmac-3.512" to select IP version.
     15
     16- clocks: Should contain phandles to the following clocks
     17- clock-names:	Should contain the following:
     18		- "stmmaceth" for the host clock - see stmmac.txt
     19		- "gmac" for the peripheral gate clock
     20
     21- oxsemi,sys-ctrl: a phandle to the system controller syscon node
     22
     23Example :
     24
     25etha: ethernet@40400000 {
     26	compatible = "oxsemi,ox820-dwmac", "snps,dwmac-3.512";
     27	reg = <0x40400000 0x2000>;
     28	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
     29		     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
     30	interrupt-names = "macirq", "eth_wake_irq";
     31	mac-address = [000000000000]; /* Filled in by U-Boot */
     32	phy-mode = "rgmii";
     33
     34	clocks = <&stdclk CLK_820_ETHA>, <&gmacclk>;
     35	clock-names = "gmac", "stmmaceth";
     36	resets = <&reset RESET_MAC>;
     37
     38	/* Regmap for sys registers */
     39	oxsemi,sys-ctrl = <&sys>;
     40
     41};