cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

qcom-emac.txt (2681B)

      1Qualcomm Technologies EMAC Gigabit Ethernet Controller
      2
      3This network controller consists of two devices: a MAC and an SGMII
      4internal PHY.  Each device is represented by a device tree node.  A phandle
      5connects the MAC node to its corresponding internal phy node.  Another
      6phandle points to the external PHY node.
      7
      8Required properties:
      9
     10MAC node:
     11- compatible : Should be "qcom,fsm9900-emac".
     12- reg : Offset and length of the register regions for the device
     13- interrupts : Interrupt number used by this controller
     14- mac-address : The 6-byte MAC address. If present, it is the default
     15	MAC address.
     16- internal-phy : phandle to the internal PHY node
     17- phy-handle : phandle the the external PHY node
     18
     19Internal PHY node:
     20- compatible : Should be "qcom,fsm9900-emac-sgmii" or "qcom,qdf2432-emac-sgmii".
     21- reg : Offset and length of the register region(s) for the device
     22- interrupts : Interrupt number used by this controller
     23
     24The external phy child node:
     25- reg : The phy address
     26
     27Example:
     28
     29FSM9900:
     30
     31soc {
     32	#address-cells = <1>;
     33	#size-cells = <1>;
     34
     35	emac0: ethernet@feb20000 {
     36		compatible = "qcom,fsm9900-emac";
     37		reg = <0xfeb20000 0x10000>,
     38		      <0xfeb36000 0x1000>;
     39		interrupts = <76>;
     40
     41		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
     42			<&gcc 6>, <&gcc 7>;
     43		clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
     44			"mdio_clk", "tx_clk", "rx_clk", "sys_clk";
     45
     46		internal-phy = <&emac_sgmii>;
     47
     48		phy-handle = <&phy0>;
     49
     50		#address-cells = <1>;
     51		#size-cells = <0>;
     52		phy0: ethernet-phy@0 {
     53			reg = <0>;
     54		};
     55
     56		pinctrl-names = "default";
     57		pinctrl-0 = <&mdio_pins_a>;
     58	};
     59
     60	emac_sgmii: ethernet@feb38000 {
     61		compatible = "qcom,fsm9900-emac-sgmii";
     62		reg = <0xfeb38000 0x1000>;
     63		interrupts = <80>;
     64	};
     65
     66	tlmm: pinctrl@fd510000 {
     67		compatible = "qcom,fsm9900-pinctrl";
     68
     69		mdio_pins_a: mdio {
     70			state {
     71				pins = "gpio123", "gpio124";
     72				function = "mdio";
     73			};
     74		};
     75	};
     76
     77
     78QDF2432:
     79
     80soc {
     81	#address-cells = <2>;
     82	#size-cells = <2>;
     83
     84	emac0: ethernet@38800000 {
     85		compatible = "qcom,fsm9900-emac";
     86		reg = <0x0 0x38800000 0x0 0x10000>,
     87		      <0x0 0x38816000 0x0 0x1000>;
     88		interrupts = <0 256 4>;
     89
     90		clocks = <&gcc 0>, <&gcc 1>, <&gcc 3>, <&gcc 4>, <&gcc 5>,
     91			 <&gcc 6>, <&gcc 7>;
     92		clock-names = "axi_clk", "cfg_ahb_clk", "high_speed_clk",
     93			"mdio_clk", "tx_clk", "rx_clk", "sys_clk";
     94
     95		internal-phy = <&emac_sgmii>;
     96
     97		phy-handle = <&phy0>;
     98
     99		#address-cells = <1>;
    100		#size-cells = <0>;
    101		phy0: ethernet-phy@4 {
    102			reg = <4>;
    103		};
    104	};
    105
    106	emac_sgmii: ethernet@410400 {
    107		compatible = "qcom,qdf2432-emac-sgmii";
    108		reg = <0x0 0x00410400 0x0 0xc00>, /* Base address */
    109		      <0x0 0x00410000 0x0 0x400>; /* Per-lane digital */
    110		interrupts = <0 254 1>;
    111	};