cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ralink,rt2880-net.txt (1438B)


      1Ralink Frame Engine Ethernet controller
      2=======================================
      3
      4The Ralink frame engine ethernet controller can be found on Ralink and
      5Mediatek SoCs (RT288x, RT3x5x, RT366x, RT388x, rt5350, mt7620, mt7621, mt76x8).
      6
      7Depending on the SoC, there is a number of ports connected to the CPU port
      8directly and/or via a (gigabit-)switch.
      9
     10* Ethernet controller node
     11
     12Required properties:
     13- compatible: Should be one of "ralink,rt2880-eth", "ralink,rt3050-eth",
     14  "ralink,rt3050-eth", "ralink,rt3883-eth", "ralink,rt5350-eth",
     15  "mediatek,mt7620-eth", "mediatek,mt7621-eth"
     16- reg: Address and length of the register set for the device
     17- interrupts: Should contain the frame engines interrupt
     18- resets: Should contain the frame engines resets
     19- reset-names: Should contain the reset names "fe". If a switch is present
     20  "esw" is also required.
     21
     22
     23* Ethernet port node
     24
     25Required properties:
     26- compatible: Should be "ralink,eth-port"
     27- reg: The number of the physical port
     28- phy-handle: reference to the node describing the phy
     29
     30Example:
     31
     32mdio-bus {
     33	...
     34	phy0: ethernet-phy@0 {
     35		phy-mode = "mii";
     36		reg = <0>;
     37	};
     38};
     39
     40ethernet@400000 {
     41	compatible = "ralink,rt2880-eth";
     42	reg = <0x00400000 10000>;
     43
     44	#address-cells = <1>;
     45	#size-cells = <0>;
     46
     47	resets = <&rstctrl 18>;
     48	reset-names = "fe";
     49
     50	interrupt-parent = <&cpuintc>;
     51	interrupts = <5>;
     52
     53	port@0 {
     54		compatible = "ralink,eth-port";
     55		reg = <0>;
     56		phy-handle = <&phy0>;
     57	};
     58
     59};