cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

smsc,lan91c111.yaml (1198B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/net/smsc,lan91c111.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Smart Mixed-Signal Connectivity (SMSC) LAN91C9x/91C1xx Controller
      8
      9maintainers:
     10  - Nicolas Pitre <nico@fluxnic.net>
     11
     12allOf:
     13  - $ref: ethernet-controller.yaml#
     14
     15properties:
     16  compatible:
     17    const: smsc,lan91c111
     18
     19  reg:
     20    maxItems: 1
     21
     22  interrupts:
     23    maxItems: 1
     24
     25  reg-shift: true
     26
     27  reg-io-width:
     28    enum: [ 1, 2, 4 ]
     29    default: 4
     30
     31  reset-gpios:
     32    description: GPIO connected to control RESET pin
     33    maxItems: 1
     34
     35  power-gpios:
     36    description: GPIO connect to control PWRDWN pin
     37    maxItems: 1
     38
     39  pxa-u16-align4:
     40    description: put in place the workaround the force all u16 writes to be
     41      32 bits aligned
     42    type: boolean
     43
     44required:
     45  - compatible
     46  - reg
     47  - interrupts
     48
     49unevaluatedProperties: false
     50
     51examples:
     52  - |
     53    #include <dt-bindings/interrupt-controller/arm-gic.h>
     54
     55    ethernet@4010000 {
     56          compatible = "smsc,lan91c111";
     57          reg = <0x40100000 0x10000>;
     58          phy-mode = "mii";
     59          interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
     60          reg-io-width = <2>;
     61    };