cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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socionext-netsec.txt (1992B)

      1* Socionext NetSec Ethernet Controller IP
      2
      3Required properties:
      4- compatible: Should be "socionext,synquacer-netsec"
      5- reg: Address and length of the control register area, followed by the
      6       address and length of the EEPROM holding the MAC address and
      7       microengine firmware
      8- interrupts: Should contain ethernet controller interrupt
      9- clocks: phandle to the PHY reference clock
     10- clock-names: Should be "phy_ref_clk"
     11- phy-mode: See ethernet.txt file in the same directory
     12- phy-handle: See ethernet.txt in the same directory.
     13
     14- mdio device tree subnode: When the Netsec has a phy connected to its local
     15		mdio, there must be device tree subnode with the following
     16		required properties:
     17
     18	- #address-cells: Must be <1>.
     19	- #size-cells: Must be <0>.
     20
     21	For each phy on the mdio bus, there must be a node with the following
     22	fields:
     23	- compatible: Refer to phy.txt
     24	- reg: phy id used to communicate to phy.
     25
     26Optional properties: (See ethernet.txt file in the same directory)
     27- dma-coherent: Boolean property, must only be present if memory
     28	accesses performed by the device are cache coherent.
     29- max-speed: See ethernet.txt in the same directory.
     30- max-frame-size: See ethernet.txt in the same directory.
     31
     32The MAC address will be determined using the optional properties
     33defined in ethernet.txt. The 'phy-mode' property is required, but may
     34be set to the empty string if the PHY configuration is programmed by
     35the firmware or set by hardware straps, and needs to be preserved.
     36
     37Example:
     38	eth0: ethernet@522d0000 {
     39		compatible = "socionext,synquacer-netsec";
     40		reg = <0 0x522d0000 0x0 0x10000>, <0 0x10000000 0x0 0x10000>;
     41		interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
     42		clocks = <&clk_netsec>;
     43		clock-names = "phy_ref_clk";
     44		phy-mode = "rgmii";
     45		max-speed = <1000>;
     46		max-frame-size = <9000>;
     47		phy-handle = <&phy1>;
     48
     49		mdio {
     50			#address-cells = <1>;
     51			#size-cells = <0>;
     52			phy1: ethernet-phy@1 {
     53				compatible = "ethernet-phy-ieee802.3-c22";
     54				reg = <1>;
     55			};
     56		};