cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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sti-dwmac.txt (2176B)

      1STMicroelectronics SoC DWMAC glue layer controller
      2
      3This file documents differences between the core properties in
      4Documentation/devicetree/bindings/net/stmmac.txt
      5and what is needed on STi platforms to program the stmmac glue logic.
      6
      7The device node has following properties.
      8
      9Required properties:
     10 - compatible	: Can be "st,stih415-dwmac", "st,stih416-dwmac",
     11   "st,stih407-dwmac", "st,stid127-dwmac".
     12 - st,syscon : Should be phandle/offset pair. The phandle to the syscon node which
     13   encompases the glue register, and the offset of the control register.
     14 - st,gmac_en: this is to enable the gmac into a dedicated sysctl control
     15   register available on STiH407 SoC.
     16 - pinctrl-0: pin-control for all the MII mode supported.
     17
     18Optional properties:
     19 - resets : phandle pointing to the system reset controller with correct
     20   reset line index for ethernet reset.
     21 - st,ext-phyclk: valid only for RMII where PHY can generate 50MHz clock or
     22   MAC can generate it.
     23 - st,tx-retime-src: This specifies which clk is wired up to the mac for
     24   retimeing tx lines. This is totally board dependent and can take one of the
     25   posssible values from "txclk", "clk_125" or "clkgen".
     26   If not passed, the internal clock will be used by default.
     27 - sti-ethclk: this is the phy clock.
     28 - sti-clkconf: this is an extra sysconfig register, available in new SoCs,
     29   to program the clk retiming.
     30 - st,gmac_en: to enable the GMAC, this only is present in some SoCs; e.g.
     31   STiH407.
     32
     33Example:
     34
     35ethernet0: dwmac@9630000 {
     36	device_type = "network";
     37	compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
     38	reg = <0x9630000 0x8000>;
     39	reg-names = "stmmaceth";
     40
     41	st,syscon = <&syscfg_sbc_reg 0x80>;
     42	st,gmac_en;
     43	resets = <&softreset STIH407_ETH1_SOFTRESET>;
     44	reset-names = "stmmaceth";
     45
     46	interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
     47		     <GIC_SPI 99 IRQ_TYPE_NONE>,
     48		     <GIC_SPI 100 IRQ_TYPE_NONE>;
     49	interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
     50
     51	snps,pbl = <32>;
     52	snps,mixed-burst;
     53
     54	pinctrl-names = "default";
     55	pinctrl-0 = <&pinctrl_rgmii1>;
     56
     57	clock-names = "stmmaceth", "sti-ethclk";
     58	clocks = <&CLK_S_C0_FLEXGEN CLK_EXT2F_A9>,
     59		 <&CLK_S_C0_FLEXGEN CLK_ETH_PHY>;
     60};