cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,dp83867.yaml (4692B)

      1# SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause)
      2# Copyright (C) 2019 Texas Instruments Incorporated
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/net/ti,dp83867.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: TI DP83867 ethernet PHY
      9
     10allOf:
     11  - $ref: "ethernet-controller.yaml#"
     12
     13maintainers:
     14  - Dan Murphy <dmurphy@ti.com>
     15
     16description: |
     17  The DP83867 device is a robust, low power, fully featured Physical Layer
     18  transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX
     19  and 1000BASE-T Ethernet protocols.
     20
     21  The DP83867 is designed for easy implementation of 10/100/1000 Mbps Ethernet
     22  LANs. It interfaces directly to twisted pair media via an external
     23  transformer. This device interfaces directly to the MAC layer through the
     24  IEEE 802.3 Standard Media Independent Interface (MII), the IEEE 802.3 Gigabit
     25  Media Independent Interface (GMII) or Reduced GMII (RGMII).
     26
     27  Specifications about the Ethernet PHY can be found at:
     28    https://www.ti.com/lit/gpn/dp83867ir
     29
     30properties:
     31  reg:
     32    maxItems: 1
     33
     34  ti,min-output-impedance:
     35    type: boolean
     36    description: |
     37       MAC Interface Impedance control to set the programmable output impedance
     38       to a minimum value (35 ohms).
     39
     40  ti,max-output-impedance:
     41    type: boolean
     42    description: |
     43      MAC Interface Impedance control to set the programmable output impedance
     44      to a maximum value (70 ohms).
     45      Note: ti,min-output-impedance and ti,max-output-impedance are mutually
     46        exclusive. When both properties are present ti,max-output-impedance
     47        takes precedence.
     48
     49  tx-fifo-depth:
     50    $ref: /schemas/types.yaml#/definitions/uint32
     51    description: |
     52       Transmitt FIFO depth see dt-bindings/net/ti-dp83867.h for values
     53
     54  rx-fifo-depth:
     55    $ref: /schemas/types.yaml#/definitions/uint32
     56    description: |
     57       Receive FIFO depth see dt-bindings/net/ti-dp83867.h for values
     58
     59  ti,clk-output-sel:
     60    $ref: /schemas/types.yaml#/definitions/uint32
     61    description: |
     62      Muxing option for CLK_OUT pin.  See dt-bindings/net/ti-dp83867.h
     63      for applicable values. The CLK_OUT pin can also be disabled by this
     64      property.  When omitted, the PHY's default will be left as is.
     65
     66  ti,rx-internal-delay:
     67    $ref: /schemas/types.yaml#/definitions/uint32
     68    description: |
     69      RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
     70      for applicable values. Required only if interface type is
     71      PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_RXID.
     72
     73  ti,tx-internal-delay:
     74    $ref: /schemas/types.yaml#/definitions/uint32
     75    description: |
     76      RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
     77      for applicable values. Required only if interface type is
     78      PHY_INTERFACE_MODE_RGMII_ID or PHY_INTERFACE_MODE_RGMII_TXID.
     79
     80        Note: If the interface type is PHY_INTERFACE_MODE_RGMII the TX/RX clock
     81          delays will be left at their default values, as set by the PHY's pin
     82          strapping. The default strapping will use a delay of 2.00 ns.  Thus
     83          PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
     84          internal delay, but as PHY_INTERFACE_MODE_RGMII_ID.  The device tree
     85          should use "rgmii-id" if internal delays are desired as this may be
     86          changed in future to cause "rgmii" mode to disable delays.
     87
     88  ti,dp83867-rxctrl-strap-quirk:
     89    type: boolean
     90    description: |
     91      This denotes the fact that the board has RX_DV/RX_CTRL pin strapped in
     92      mode 1 or 2. To ensure PHY operation, there are specific actions that
     93      software needs to take when this pin is strapped in these modes.
     94      See data manual for details.
     95
     96  ti,sgmii-ref-clock-output-enable:
     97    type: boolean
     98    description: |
     99      This denotes which SGMII configuration is used (4 or 6-wire modes).
    100      Some MACs work with differential SGMII clock. See data manual for details.
    101
    102  ti,fifo-depth:
    103    deprecated: true
    104    $ref: /schemas/types.yaml#/definitions/uint32
    105    description: |
    106      Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h for applicable
    107      values.
    108
    109required:
    110  - reg
    111
    112unevaluatedProperties: false
    113
    114examples:
    115  - |
    116    #include <dt-bindings/net/ti-dp83867.h>
    117    mdio0 {
    118      #address-cells = <1>;
    119      #size-cells = <0>;
    120      ethphy0: ethernet-phy@0 {
    121        reg = <0>;
    122        tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
    123        rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
    124        ti,max-output-impedance;
    125        ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_RCLK>;
    126        ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
    127        ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
    128      };
    129    };