cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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wiznet,w5x00.txt (1648B)

      1* Wiznet w5x00
      2
      3This is a standalone 10/100 MBit Ethernet controller with SPI interface.
      4
      5For each device connected to a SPI bus, define a child node within
      6the SPI master node.
      7
      8Required properties:
      9- compatible: Should be one of the following strings:
     10	      "wiznet,w5100"
     11	      "wiznet,w5200"
     12	      "wiznet,w5500"
     13- reg: Specify the SPI chip select the chip is wired to.
     14- interrupts: Specify the interrupt index within the interrupt controller (referred
     15              to above in interrupt-parent) and interrupt type. w5x00 natively
     16              generates falling edge interrupts, however, additional board logic
     17              might invert the signal.
     18- pinctrl-names: List of assigned state names, see pinctrl binding documentation.
     19- pinctrl-0: List of phandles to configure the GPIO pin used as interrupt line,
     20             see also generic and your platform specific pinctrl binding
     21             documentation.
     22
     23Optional properties:
     24- spi-max-frequency: Maximum frequency of the SPI bus when accessing the w5500.
     25  According to the w5500 datasheet, the chip allows a maximum of 80 MHz, however,
     26  board designs may need to limit this value.
     27- local-mac-address: See ethernet.txt in the same directory.
     28
     29
     30Example (for Raspberry Pi with pin control stuff for GPIO irq):
     31
     32&spi {
     33	ethernet@0: w5500@0 {
     34		compatible = "wiznet,w5500";
     35		reg = <0>;
     36		pinctrl-names = "default";
     37		pinctrl-0 = <&eth1_pins>;
     38		interrupt-parent = <&gpio>;
     39		interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
     40		spi-max-frequency = <30000000>;
     41	};
     42};
     43
     44&gpio {
     45	eth1_pins: eth1_pins {
     46		brcm,pins = <25>;
     47		brcm,function = <0>; /* in */
     48		brcm,pull = <0>; /* none */
     49	};
     50};