cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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nvmem.yaml (2546B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/nvmem/nvmem.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: NVMEM (Non Volatile Memory) Device Tree Bindings
      8
      9maintainers:
     10  - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
     11
     12description: |
     13  This binding is intended to represent the location of hardware
     14  configuration data stored in NVMEMs like eeprom, efuses and so on.
     15
     16  On a significant proportion of boards, the manufacturer has stored
     17  some data on NVMEM, for the OS to be able to retrieve these
     18  information and act upon it. Obviously, the OS has to know about
     19  where to retrieve these data from, and where they are stored on the
     20  storage device.
     21
     22properties:
     23  "#address-cells":
     24    const: 1
     25
     26  "#size-cells":
     27    const: 1
     28
     29  read-only:
     30    $ref: /schemas/types.yaml#/definitions/flag
     31    description:
     32      Mark the provider as read only.
     33
     34  wp-gpios:
     35    description:
     36      GPIO to which the write-protect pin of the chip is connected.
     37      The write-protect GPIO is asserted, when it's driven high
     38      (logical '1') to block the write operation. It's deasserted,
     39      when it's driven low (logical '0') to allow writing.
     40    maxItems: 1
     41
     42patternProperties:
     43  "@[0-9a-f]+(,[0-7])?$":
     44    type: object
     45
     46    properties:
     47      reg:
     48        maxItems: 1
     49        description:
     50          Offset and size in bytes within the storage device.
     51
     52      bits:
     53        $ref: /schemas/types.yaml#/definitions/uint32-array
     54        items:
     55          - minimum: 0
     56            maximum: 7
     57            description:
     58              Offset in bit within the address range specified by reg.
     59          - minimum: 1
     60            description:
     61              Size in bit within the address range specified by reg.
     62
     63additionalProperties: true
     64
     65examples:
     66  - |
     67      #include <dt-bindings/gpio/gpio.h>
     68
     69      qfprom: eeprom@700000 {
     70          #address-cells = <1>;
     71          #size-cells = <1>;
     72          reg = <0x00700000 0x100000>;
     73
     74          wp-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
     75
     76          /* ... */
     77
     78          /* Data cells */
     79          tsens_calibration: calib@404 {
     80              reg = <0x404 0x10>;
     81          };
     82
     83          tsens_calibration_bckp: calib_bckp@504 {
     84              reg = <0x504 0x11>;
     85              bits = <6 128>;
     86          };
     87
     88          pvs_version: pvs-version@6 {
     89              reg = <0x6 0x2>;
     90              bits = <7 2>;
     91          };
     92
     93          speed_bin: speed-bin@c{
     94              reg = <0xc 0x1>;
     95              bits = <2 3>;
     96          };
     97      };
     98
     99...