cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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opp-v1.yaml (1379B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/opp/opp-v1.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Generic OPP (Operating Performance Points) v1 Bindings
      8
      9maintainers:
     10  - Viresh Kumar <viresh.kumar@linaro.org>
     11
     12description: |+
     13  Devices work at voltage-current-frequency combinations and some implementations
     14  have the liberty of choosing these. These combinations are called Operating
     15  Performance Points aka OPPs. This document defines bindings for these OPPs
     16  applicable across wide range of devices. For illustration purpose, this document
     17  uses CPU as a device.
     18
     19  This binding only supports voltage-frequency pairs.
     20
     21select: true
     22
     23properties:
     24  operating-points:
     25    $ref: /schemas/types.yaml#/definitions/uint32-matrix
     26    items:
     27      items:
     28        - description: Frequency in kHz
     29        - description: Voltage for OPP in uV
     30
     31
     32additionalProperties: true
     33examples:
     34  - |
     35    cpus {
     36        #address-cells = <1>;
     37        #size-cells = <0>;
     38
     39        cpu@0 {
     40            compatible = "arm,cortex-a9";
     41            device_type = "cpu";
     42            reg = <0>;
     43            next-level-cache = <&L2>;
     44            operating-points =
     45                /* kHz    uV */
     46                <792000 1100000>,
     47                <396000 950000>,
     48                <198000 850000>;
     49        };
     50    };
     51...