cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti-omap5-opp-supply.txt (2298B)


      1Texas Instruments OMAP compatible OPP supply description
      2
      3OMAP5, DRA7, and AM57 family of SoCs have Class0 AVS eFuse registers which
      4contain data that can be used to adjust voltages programmed for some of their
      5supplies for more efficient operation. This binding provides the information
      6needed to read these values and use them to program the main regulator during
      7an OPP transitions.
      8
      9Also, some supplies may have an associated vbb-supply which is an Adaptive Body
     10Bias regulator which much be transitioned in a specific sequence with regards
     11to the vdd-supply and clk when making an OPP transition. By supplying two
     12regulators to the device that will undergo OPP transitions we can make use
     13of the multi regulator binding that is part of the OPP core described here [1]
     14to describe both regulators needed by the platform.
     15
     16[1] Documentation/devicetree/bindings/opp/opp-v2.yaml
     17
     18Required Properties for Device Node:
     19- vdd-supply: phandle to regulator controlling VDD supply
     20- vbb-supply: phandle to regulator controlling Body Bias supply
     21	      (Usually Adaptive Body Bias regulator)
     22
     23Required Properties for opp-supply node:
     24- compatible: Should be one of:
     25	"ti,omap-opp-supply" - basic OPP supply controlling VDD and VBB
     26	"ti,omap5-opp-supply" - OMAP5+ optimized voltages in efuse(class0)VDD
     27			    along with VBB
     28	"ti,omap5-core-opp-supply" - OMAP5+ optimized voltages in efuse(class0) VDD
     29			    but no VBB.
     30- reg: Address and length of the efuse register set for the device (mandatory
     31	only for "ti,omap5-opp-supply")
     32- ti,efuse-settings: An array of u32 tuple items providing information about
     33	optimized efuse configuration. Each item consists of the following:
     34	volt: voltage in uV - reference voltage (OPP voltage)
     35	efuse_offseet: efuse offset from reg where the optimized voltage is stored.
     36- ti,absolute-max-voltage-uv: absolute maximum voltage for the OPP supply.
     37
     38Example:
     39
     40/* Device Node (CPU)  */
     41cpus {
     42	cpu0: cpu@0 {
     43		device_type = "cpu";
     44
     45		...
     46
     47		vdd-supply = <&vcc>;
     48		vbb-supply = <&abb_mpu>;
     49	};
     50};
     51
     52/* OMAP OPP Supply with Class0 registers */
     53opp_supply_mpu: opp_supply@4a003b20 {
     54	compatible = "ti,omap5-opp-supply";
     55	reg = <0x4a003b20 0x8>;
     56	ti,efuse-settings = <
     57	/* uV   offset */
     58	1060000 0x0
     59	1160000 0x4
     60	1210000 0x8
     61	>;
     62	ti,absolute-max-voltage-uv = <1500000>;
     63};