cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

altera-pcie-msi.txt (856B)


      1* Altera PCIe MSI controller
      2
      3Required properties:
      4- compatible:	should contain "altr,msi-1.0"
      5- reg:		specifies the physical base address of the controller and
      6		the length of the memory mapped region.
      7- reg-names:	must include the following entries:
      8		"csr": CSR registers
      9		"vector_slave": vectors slave port region
     10- interrupts:	specifies the interrupt source of the parent interrupt
     11		controller. The format of the interrupt specifier depends on the
     12		parent interrupt controller.
     13- num-vectors:	number of vectors, range 1 to 32.
     14- msi-controller:	indicates that this is MSI controller node
     15
     16
     17Example
     18msi0: msi@0xFF200000 {
     19	compatible = "altr,msi-1.0";
     20	reg = <0xFF200000 0x00000010
     21		0xFF200010 0x00000080>;
     22	reg-names = "csr", "vector_slave";
     23	interrupt-parent = <&hps_0_arm_gic_0>;
     24	interrupts = <0 42 4>;
     25	msi-controller;
     26	num-vectors = <32>;
     27};