cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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pci-rcar-gen2.txt (2783B)

      1Renesas AHB to PCI bridge
      2-------------------------
      3
      4This is the bridge used internally to connect the USB controllers to the
      5AHB. There is one bridge instance per USB port connected to the internal
      6OHCI and EHCI controllers.
      7
      8Required properties:
      9- compatible: "renesas,pci-r8a7742" for the R8A7742 SoC;
     10	      "renesas,pci-r8a7743" for the R8A7743 SoC;
     11	      "renesas,pci-r8a7744" for the R8A7744 SoC;
     12	      "renesas,pci-r8a7745" for the R8A7745 SoC;
     13	      "renesas,pci-r8a7790" for the R8A7790 SoC;
     14	      "renesas,pci-r8a7791" for the R8A7791 SoC;
     15	      "renesas,pci-r8a7793" for the R8A7793 SoC;
     16	      "renesas,pci-r8a7794" for the R8A7794 SoC;
     17	      "renesas,pci-rcar-gen2" for a generic R-Car Gen2 or
     18				      RZ/G1 compatible device.
     19
     20
     21	      When compatible with the generic version, nodes must list the
     22	      SoC-specific version corresponding to the platform first
     23	      followed by the generic version.
     24
     25- reg:	A list of physical regions to access the device: the first is
     26	the operational registers for the OHCI/EHCI controllers and the
     27	second is for the bridge configuration and control registers.
     28- interrupts: interrupt for the device.
     29- clocks: The reference to the device clock.
     30- bus-range: The PCI bus number range; as this is a single bus, the range
     31	     should be specified as the same value twice.
     32- #address-cells: must be 3.
     33- #size-cells: must be 2.
     34- #interrupt-cells: must be 1.
     35- interrupt-map: standard property used to define the mapping of the PCI
     36  interrupts to the GIC interrupts.
     37- interrupt-map-mask: standard property that helps to define the interrupt
     38  mapping.
     39
     40Optional properties:
     41- dma-ranges: a single range for the inbound memory region. If not supplied,
     42  defaults to 1GiB at 0x40000000. Note there are hardware restrictions on the
     43  allowed combinations of address and size.
     44
     45Example SoC configuration:
     46
     47	pci0: pci@ee090000  {
     48		compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
     49		clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
     50		reg = <0x0 0xee090000 0x0 0xc00>,
     51		      <0x0 0xee080000 0x0 0x1100>;
     52		interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
     53		status = "disabled";
     54
     55		bus-range = <0 0>;
     56		#address-cells = <3>;
     57		#size-cells = <2>;
     58		#interrupt-cells = <1>;
     59		dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>;
     60		interrupt-map-mask = <0xff00 0 0 0x7>;
     61		interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
     62				 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
     63				 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
     64
     65		usb@1,0 {
     66			reg = <0x800 0 0 0 0>;
     67			phys = <&usb0 0>;
     68			phy-names = "usb";
     69		};
     70
     71		usb@2,0 {
     72			reg = <0x1000 0 0 0 0>;
     73			phys = <&usb0 0>;
     74			phy-names = "usb";
     75		};
     76	};
     77
     78Example board setup:
     79
     80&pci0 {
     81	status = "okay";
     82	pinctrl-0 = <&usb0_pins>;
     83	pinctrl-names = "default";
     84};