cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,pcie-ep.yaml (3974B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pci/qcom,pcie-ep.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Qualcomm PCIe Endpoint Controller binding
      8
      9maintainers:
     10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
     11
     12allOf:
     13  - $ref: "pci-ep.yaml#"
     14
     15properties:
     16  compatible:
     17    const: qcom,sdx55-pcie-ep
     18
     19  reg:
     20    items:
     21      - description: Qualcomm-specific PARF configuration registers
     22      - description: DesignWare PCIe registers
     23      - description: External local bus interface registers
     24      - description: Address Translation Unit (ATU) registers
     25      - description: Memory region used to map remote RC address space
     26      - description: BAR memory region
     27
     28  reg-names:
     29    items:
     30      - const: parf
     31      - const: dbi
     32      - const: elbi
     33      - const: atu
     34      - const: addr_space
     35      - const: mmio
     36
     37  clocks:
     38    items:
     39      - description: PCIe Auxiliary clock
     40      - description: PCIe CFG AHB clock
     41      - description: PCIe Master AXI clock
     42      - description: PCIe Slave AXI clock
     43      - description: PCIe Slave Q2A AXI clock
     44      - description: PCIe Sleep clock
     45      - description: PCIe Reference clock
     46
     47  clock-names:
     48    items:
     49      - const: aux
     50      - const: cfg
     51      - const: bus_master
     52      - const: bus_slave
     53      - const: slave_q2a
     54      - const: sleep
     55      - const: ref
     56
     57  qcom,perst-regs:
     58    description: Reference to a syscon representing TCSR followed by the two
     59                 offsets within syscon for Perst enable and Perst separation
     60                 enable registers
     61    $ref: "/schemas/types.yaml#/definitions/phandle-array"
     62    items:
     63      minItems: 3
     64      maxItems: 3
     65
     66  interrupts:
     67    items:
     68      - description: PCIe Global interrupt
     69      - description: PCIe Doorbell interrupt
     70
     71  interrupt-names:
     72    items:
     73      - const: global
     74      - const: doorbell
     75
     76  reset-gpios:
     77    description: GPIO used as PERST# input signal
     78    maxItems: 1
     79
     80  wake-gpios:
     81    description: GPIO used as WAKE# output signal
     82    maxItems: 1
     83
     84  resets:
     85    maxItems: 1
     86
     87  reset-names:
     88    const: core
     89
     90  power-domains:
     91    maxItems: 1
     92
     93  phys:
     94    maxItems: 1
     95
     96  phy-names:
     97    const: pciephy
     98
     99  num-lanes:
    100    default: 2
    101
    102required:
    103  - compatible
    104  - reg
    105  - reg-names
    106  - clocks
    107  - clock-names
    108  - qcom,perst-regs
    109  - interrupts
    110  - interrupt-names
    111  - reset-gpios
    112  - resets
    113  - reset-names
    114  - power-domains
    115
    116unevaluatedProperties: false
    117
    118examples:
    119  - |
    120    #include <dt-bindings/clock/qcom,gcc-sdx55.h>
    121    #include <dt-bindings/gpio/gpio.h>
    122    #include <dt-bindings/interrupt-controller/arm-gic.h>
    123    pcie_ep: pcie-ep@40000000 {
    124        compatible = "qcom,sdx55-pcie-ep";
    125        reg = <0x01c00000 0x3000>,
    126              <0x40000000 0xf1d>,
    127              <0x40000f20 0xc8>,
    128              <0x40001000 0x1000>,
    129              <0x40002000 0x1000>,
    130              <0x01c03000 0x3000>;
    131        reg-names = "parf", "dbi", "elbi", "atu", "addr_space",
    132                    "mmio";
    133
    134        clocks = <&gcc GCC_PCIE_AUX_CLK>,
    135             <&gcc GCC_PCIE_CFG_AHB_CLK>,
    136             <&gcc GCC_PCIE_MSTR_AXI_CLK>,
    137             <&gcc GCC_PCIE_SLV_AXI_CLK>,
    138             <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
    139             <&gcc GCC_PCIE_SLEEP_CLK>,
    140             <&gcc GCC_PCIE_0_CLKREF_CLK>;
    141        clock-names = "aux", "cfg", "bus_master", "bus_slave",
    142                      "slave_q2a", "sleep", "ref";
    143
    144        qcom,perst-regs = <&tcsr 0xb258 0xb270>;
    145
    146        interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
    147                     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
    148        interrupt-names = "global", "doorbell";
    149        reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
    150        wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>;
    151        resets = <&gcc GCC_PCIE_BCR>;
    152        reset-names = "core";
    153        power-domains = <&gcc PCIE_GDSC>;
    154        phys = <&pcie0_lane>;
    155        phy-names = "pciephy";
    156        max-link-speed = <3>;
    157        num-lanes = <2>;
    158    };