cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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socionext,uniphier-pcie.yaml (2690B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Socionext UniPhier PCIe host controller
      8
      9description: |
     10  UniPhier PCIe host controller is based on the Synopsys DesignWare
     11  PCI core. It shares common features with the PCIe DesignWare core and
     12  inherits common properties defined in
     13  Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
     14
     15maintainers:
     16  - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
     17
     18allOf:
     19  - $ref: /schemas/pci/snps,dw-pcie.yaml#
     20
     21properties:
     22  compatible:
     23    enum:
     24      - socionext,uniphier-pcie
     25
     26  reg:
     27    minItems: 3
     28    maxItems: 4
     29
     30  reg-names:
     31    minItems: 3
     32    items:
     33      - const: dbi
     34      - const: link
     35      - const: config
     36      - const: atu
     37
     38  clocks:
     39    maxItems: 1
     40
     41  resets:
     42    maxItems: 1
     43
     44  num-viewport: true
     45
     46  num-lanes: true
     47
     48  phys:
     49    maxItems: 1
     50
     51  phy-names:
     52    const: pcie-phy
     53
     54  interrupt-controller:
     55    type: object
     56    additionalProperties: false
     57
     58    properties:
     59      interrupt-controller: true
     60
     61      '#interrupt-cells':
     62        const: 1
     63
     64      interrupts:
     65        maxItems: 1
     66
     67required:
     68  - compatible
     69  - reg
     70  - reg-names
     71  - clocks
     72  - resets
     73
     74unevaluatedProperties: false
     75
     76examples:
     77  - |
     78    bus {
     79        gic: interrupt-controller {
     80            interrupt-controller;
     81            #interrupt-cells = <3>;
     82        };
     83    };
     84
     85    pcie: pcie@66000000 {
     86        compatible = "socionext,uniphier-pcie";
     87        reg-names = "dbi", "link", "config";
     88        reg = <0x66000000 0x1000>, <0x66010000 0x10000>, <0x2fff0000 0x10000>;
     89        #address-cells = <3>;
     90        #size-cells = <2>;
     91        clocks = <&sys_clk 24>;
     92        resets = <&sys_rst 24>;
     93        num-lanes = <1>;
     94        num-viewport = <1>;
     95        bus-range = <0x0 0xff>;
     96        device_type = "pci";
     97        ranges = <0x81000000 0 0x00000000  0x2ffe0000  0 0x00010000>,
     98                 <0x82000000 0 0x00000000  0x20000000  0 0x0ffe0000>;
     99        phy-names = "pcie-phy";
    100        phys = <&pcie_phy>;
    101        #interrupt-cells = <1>;
    102        interrupt-names = "dma", "msi";
    103        interrupt-parent = <&gic>;
    104        interrupts = <0 224 4>, <0 225 4>;
    105        interrupt-map-mask = <0 0 0  7>;
    106        interrupt-map = <0 0 0  1  &pcie_intc 0>,
    107                        <0 0 0  2  &pcie_intc 1>,
    108                        <0 0 0  3  &pcie_intc 2>,
    109                        <0 0 0  4  &pcie_intc 3>;
    110
    111        pcie_intc: interrupt-controller {
    112            interrupt-controller;
    113            #interrupt-cells = <1>;
    114            interrupt-parent = <&gic>;
    115            interrupts = <0 226 4>;
    116        };
    117    };