cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,am65-pci-host.yaml (2660B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
      3%YAML 1.2
      4---
      5$id: http://devicetree.org/schemas/pci/ti,am65-pci-host.yaml#
      6$schema: http://devicetree.org/meta-schemas/core.yaml#
      7
      8title: TI AM65 PCI Host
      9
     10maintainers:
     11  - Kishon Vijay Abraham I <kishon@ti.com>
     12
     13allOf:
     14  - $ref: /schemas/pci/pci-bus.yaml#
     15
     16properties:
     17  compatible:
     18    enum:
     19      - ti,am654-pcie-rc
     20      - ti,keystone-pcie
     21
     22  reg:
     23    maxItems: 4
     24
     25  reg-names:
     26    items:
     27      - const: app
     28      - const: dbics
     29      - const: config
     30      - const: atu
     31
     32  interrupts:
     33    maxItems: 1
     34
     35  power-domains:
     36    maxItems: 1
     37
     38  ti,syscon-pcie-id:
     39    $ref: /schemas/types.yaml#/definitions/phandle-array
     40    items:
     41      - items:
     42          - description: Phandle to the SYSCON entry
     43          - description: pcie_device_id register offset within SYSCON
     44    description: Phandle to the SYSCON entry required for getting PCIe device/vendor ID
     45
     46  ti,syscon-pcie-mode:
     47    $ref: /schemas/types.yaml#/definitions/phandle-array
     48    items:
     49      - items:
     50          - description: Phandle to the SYSCON entry
     51          - description: pcie_ctrl register offset within SYSCON
     52    description: Phandle to the SYSCON entry required for configuring PCIe in RC or EP mode.
     53
     54  msi-map: true
     55
     56  dma-coherent: true
     57
     58required:
     59  - compatible
     60  - reg
     61  - reg-names
     62  - max-link-speed
     63  - ti,syscon-pcie-id
     64  - ti,syscon-pcie-mode
     65  - ranges
     66
     67if:
     68  properties:
     69    compatible:
     70      enum:
     71        - ti,am654-pcie-rc
     72then:
     73  required:
     74    - dma-coherent
     75    - power-domains
     76    - msi-map
     77
     78unevaluatedProperties: false
     79
     80examples:
     81  - |
     82    #include <dt-bindings/interrupt-controller/arm-gic.h>
     83    #include <dt-bindings/interrupt-controller/irq.h>
     84    #include <dt-bindings/soc/ti,sci_pm_domain.h>
     85
     86    pcie0_rc: pcie@5500000 {
     87        compatible = "ti,am654-pcie-rc";
     88        reg =  <0x5500000 0x1000>,
     89               <0x5501000 0x1000>,
     90               <0x10000000 0x2000>,
     91               <0x5506000 0x1000>;
     92        reg-names = "app", "dbics", "config", "atu";
     93        power-domains = <&k3_pds 120 TI_SCI_PD_EXCLUSIVE>;
     94        #address-cells = <3>;
     95        #size-cells = <2>;
     96        ranges = <0x81000000 0 0          0x10020000 0 0x00010000>,
     97                 <0x82000000 0 0x10030000 0x10030000 0 0x07FD0000>;
     98        ti,syscon-pcie-id = <&scm_conf 0x0210>;
     99        ti,syscon-pcie-mode = <&scm_conf 0x4060>;
    100        bus-range = <0x0 0xff>;
    101        max-link-speed = <2>;
    102        dma-coherent;
    103        interrupts = <GIC_SPI 340 IRQ_TYPE_EDGE_RISING>;
    104        msi-map = <0x0 &gic_its 0x0 0x10000>;
    105        device_type = "pci";
    106    };