cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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ti,j721e-pci-ep.yaml (2535B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/pci/ti,j721e-pci-ep.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: TI J721E PCI EP (PCIe Wrapper)
      9
     10maintainers:
     11  - Kishon Vijay Abraham I <kishon@ti.com>
     12
     13allOf:
     14  - $ref: "cdns-pcie-ep.yaml#"
     15
     16properties:
     17  compatible:
     18    oneOf:
     19      - const: ti,j721e-pcie-ep
     20      - description: PCIe EP controller in AM64
     21        items:
     22          - const: ti,am64-pcie-ep
     23          - const: ti,j721e-pcie-ep
     24      - description: PCIe EP controller in J7200
     25        items:
     26          - const: ti,j7200-pcie-ep
     27          - const: ti,j721e-pcie-ep
     28
     29  reg:
     30    maxItems: 4
     31
     32  reg-names:
     33    items:
     34      - const: intd_cfg
     35      - const: user_cfg
     36      - const: reg
     37      - const: mem
     38
     39  ti,syscon-pcie-ctrl:
     40    $ref: /schemas/types.yaml#/definitions/phandle-array
     41    items:
     42      - items:
     43          - description: Phandle to the SYSCON entry
     44          - description: pcie_ctrl register offset within SYSCON
     45    description: Specifier for configuring PCIe mode and link speed.
     46
     47  power-domains:
     48    maxItems: 1
     49
     50  clocks:
     51    maxItems: 1
     52    description: clock-specifier to represent input to the PCIe
     53
     54  clock-names:
     55    items:
     56      - const: fck
     57
     58  dma-coherent:
     59    description: Indicates that the PCIe IP block can ensure the coherency
     60
     61required:
     62  - compatible
     63  - reg
     64  - reg-names
     65  - ti,syscon-pcie-ctrl
     66  - max-link-speed
     67  - num-lanes
     68  - power-domains
     69  - clocks
     70  - clock-names
     71  - max-functions
     72  - phys
     73  - phy-names
     74
     75unevaluatedProperties: false
     76
     77examples:
     78  - |
     79    #include <dt-bindings/soc/ti,sci_pm_domain.h>
     80
     81    bus {
     82        #address-cells = <2>;
     83        #size-cells = <2>;
     84
     85        pcie0_ep: pcie-ep@d000000 {
     86           compatible = "ti,j721e-pcie-ep";
     87           reg = <0x00 0x02900000 0x00 0x1000>,
     88                 <0x00 0x02907000 0x00 0x400>,
     89                 <0x00 0x0d000000 0x00 0x00800000>,
     90                 <0x00 0x10000000 0x00 0x08000000>;
     91           reg-names = "intd_cfg", "user_cfg", "reg", "mem";
     92           ti,syscon-pcie-ctrl = <&pcie0_ctrl 0x4070>;
     93           max-link-speed = <3>;
     94           num-lanes = <2>;
     95           power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
     96           clocks = <&k3_clks 239 1>;
     97           clock-names = "fck";
     98           max-functions = /bits/ 8 <6>;
     99           dma-coherent;
    100           phys = <&serdes0_pcie_link>;
    101           phy-names = "pcie-phy";
    102       };
    103    };