cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xilinx-versal-cpm.yaml (2878B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pci/xilinx-versal-cpm.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: CPM Host Controller device tree for Xilinx Versal SoCs
      8
      9maintainers:
     10  - Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
     11
     12allOf:
     13  - $ref: /schemas/pci/pci-bus.yaml#
     14
     15properties:
     16  compatible:
     17    const: xlnx,versal-cpm-host-1.00
     18
     19  reg:
     20    items:
     21      - description: CPM system level control and status registers.
     22      - description: Configuration space region and bridge registers.
     23
     24  reg-names:
     25    items:
     26      - const: cpm_slcr
     27      - const: cfg
     28
     29  interrupts:
     30    maxItems: 1
     31
     32  msi-map:
     33    description:
     34      Maps a Requester ID to an MSI controller and associated MSI sideband data.
     35
     36  ranges:
     37    maxItems: 2
     38
     39  "#interrupt-cells":
     40    const: 1
     41
     42  interrupt-controller:
     43    description: Interrupt controller node for handling legacy PCI interrupts.
     44    type: object
     45    properties:
     46      "#address-cells":
     47        const: 0
     48      "#interrupt-cells":
     49        const: 1
     50      "interrupt-controller": true
     51    additionalProperties: false
     52
     53required:
     54  - reg
     55  - reg-names
     56  - "#interrupt-cells"
     57  - interrupts
     58  - interrupt-map
     59  - interrupt-map-mask
     60  - bus-range
     61  - msi-map
     62  - interrupt-controller
     63
     64unevaluatedProperties: false
     65
     66examples:
     67  - |
     68
     69    versal {
     70               #address-cells = <2>;
     71               #size-cells = <2>;
     72               cpm_pcie: pcie@fca10000 {
     73                       compatible = "xlnx,versal-cpm-host-1.00";
     74                       device_type = "pci";
     75                       #address-cells = <3>;
     76                       #interrupt-cells = <1>;
     77                       #size-cells = <2>;
     78                       interrupts = <0 72 4>;
     79                       interrupt-parent = <&gic>;
     80                       interrupt-map-mask = <0 0 0 7>;
     81                       interrupt-map = <0 0 0 1 &pcie_intc_0 0>,
     82                                       <0 0 0 2 &pcie_intc_0 1>,
     83                                       <0 0 0 3 &pcie_intc_0 2>,
     84                                       <0 0 0 4 &pcie_intc_0 3>;
     85                       bus-range = <0x00 0xff>;
     86                       ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
     87                                <0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
     88                       msi-map = <0x0 &its_gic 0x0 0x10000>;
     89                       reg = <0x0 0xfca10000 0x0 0x1000>,
     90                             <0x6 0x00000000 0x0 0x10000000>;
     91                       reg-names = "cpm_slcr", "cfg";
     92                       pcie_intc_0: interrupt-controller {
     93                               #address-cells = <0>;
     94                               #interrupt-cells = <1>;
     95                               interrupt-controller;
     96                       };
     97               };
     98    };