cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl-imx-ddr.yaml (1135B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/perf/fsl-imx-ddr.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale(NXP) IMX8 DDR performance monitor
      8
      9maintainers:
     10  - Frank Li <frank.li@nxp.com>
     11
     12properties:
     13  compatible:
     14    oneOf:
     15      - enum:
     16          - fsl,imx8-ddr-pmu
     17          - fsl,imx8m-ddr-pmu
     18          - fsl,imx8mq-ddr-pmu
     19          - fsl,imx8mm-ddr-pmu
     20          - fsl,imx8mn-ddr-pmu
     21          - fsl,imx8mp-ddr-pmu
     22      - items:
     23          - enum:
     24              - fsl,imx8mm-ddr-pmu
     25              - fsl,imx8mn-ddr-pmu
     26              - fsl,imx8mq-ddr-pmu
     27              - fsl,imx8mp-ddr-pmu
     28          - const: fsl,imx8m-ddr-pmu
     29
     30  reg:
     31    maxItems: 1
     32
     33  interrupts:
     34    maxItems: 1
     35
     36required:
     37  - compatible
     38  - reg
     39  - interrupts
     40
     41additionalProperties: false
     42
     43examples:
     44  - |
     45    #include <dt-bindings/interrupt-controller/arm-gic.h>
     46
     47    ddr-pmu@5c020000 {
     48        compatible = "fsl,imx8-ddr-pmu";
     49        reg = <0x5c020000 0x10000>;
     50        interrupt-parent = <&gic>;
     51        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
     52    };