cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun5i-a13-usb-phy.yaml (2211B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/allwinner,sun5i-a13-usb-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A13 USB PHY Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  "#phy-cells":
     15    const: 1
     16
     17  compatible:
     18    const: allwinner,sun5i-a13-usb-phy
     19
     20  reg:
     21    items:
     22      - description: PHY Control registers
     23      - description: PHY PMU1 registers
     24
     25  reg-names:
     26    items:
     27      - const: phy_ctrl
     28      - const: pmu1
     29
     30  clocks:
     31    maxItems: 1
     32    description: USB OTG PHY bus clock
     33
     34  clock-names:
     35    const: usb_phy
     36
     37  resets:
     38    items:
     39      - description: USB OTG reset
     40      - description: USB Host 1 Controller reset
     41
     42  reset-names:
     43    items:
     44      - const: usb0_reset
     45      - const: usb1_reset
     46
     47  usb0_id_det-gpios:
     48    maxItems: 1
     49    description: GPIO to the USB OTG ID pin
     50
     51  usb0_vbus_det-gpios:
     52    maxItems: 1
     53    description: GPIO to the USB OTG VBUS detect pin
     54
     55  usb0_vbus_power-supply:
     56    description: Power supply to detect the USB OTG VBUS
     57
     58  usb0_vbus-supply:
     59    description: Regulator controlling USB OTG VBUS
     60
     61  usb1_vbus-supply:
     62    description: Regulator controlling USB1 Host controller
     63
     64required:
     65  - "#phy-cells"
     66  - compatible
     67  - clocks
     68  - clock-names
     69  - reg
     70  - reg-names
     71  - resets
     72  - reset-names
     73
     74additionalProperties: false
     75
     76examples:
     77  - |
     78    #include <dt-bindings/gpio/gpio.h>
     79    #include <dt-bindings/clock/sun5i-ccu.h>
     80    #include <dt-bindings/reset/sun5i-ccu.h>
     81
     82    phy@1c13400 {
     83        #phy-cells = <1>;
     84        compatible = "allwinner,sun5i-a13-usb-phy";
     85        reg = <0x01c13400 0x10>, <0x01c14800 0x4>;
     86        reg-names = "phy_ctrl", "pmu1";
     87        clocks = <&ccu CLK_USB_PHY0>;
     88        clock-names = "usb_phy";
     89        resets = <&ccu RST_USB_PHY0>, <&ccu RST_USB_PHY1>;
     90        reset-names = "usb0_reset", "usb1_reset";
     91        usb0_id_det-gpios = <&pio 6 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>; /* PG2 */
     92        usb0_vbus_det-gpios = <&pio 6 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* PG1 */
     93        usb0_vbus-supply = <&reg_usb0_vbus>;
     94        usb1_vbus-supply = <&reg_usb1_vbus>;
     95    };