cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun8i-h3-usb-phy.yaml (3580B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/allwinner,sun8i-h3-usb-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner H3 USB PHY Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  "#phy-cells":
     15    const: 1
     16
     17  compatible:
     18    enum:
     19      - allwinner,sun8i-h3-usb-phy
     20      - allwinner,sun50i-h616-usb-phy
     21
     22  reg:
     23    items:
     24      - description: PHY Control registers
     25      - description: PHY PMU0 registers
     26      - description: PHY PMU1 registers
     27      - description: PHY PMU2 registers
     28      - description: PHY PMU3 registers
     29
     30  reg-names:
     31    items:
     32      - const: phy_ctrl
     33      - const: pmu0
     34      - const: pmu1
     35      - const: pmu2
     36      - const: pmu3
     37
     38  clocks:
     39    items:
     40      - description: USB OTG PHY bus clock
     41      - description: USB Host 0 PHY bus clock
     42      - description: USB Host 1 PHY bus clock
     43      - description: USB Host 2 PHY bus clock
     44
     45  clock-names:
     46    items:
     47      - const: usb0_phy
     48      - const: usb1_phy
     49      - const: usb2_phy
     50      - const: usb3_phy
     51
     52  resets:
     53    items:
     54      - description: USB OTG reset
     55      - description: USB Host 1 Controller reset
     56      - description: USB Host 2 Controller reset
     57      - description: USB Host 3 Controller reset
     58
     59  reset-names:
     60    items:
     61      - const: usb0_reset
     62      - const: usb1_reset
     63      - const: usb2_reset
     64      - const: usb3_reset
     65
     66  usb0_id_det-gpios:
     67    maxItems: 1
     68    description: GPIO to the USB OTG ID pin
     69
     70  usb0_vbus_det-gpios:
     71    maxItems: 1
     72    description: GPIO to the USB OTG VBUS detect pin
     73
     74  usb0_vbus_power-supply:
     75    description: Power supply to detect the USB OTG VBUS
     76
     77  usb0_vbus-supply:
     78    description: Regulator controlling USB OTG VBUS
     79
     80  usb1_vbus-supply:
     81    description: Regulator controlling USB1 Host controller
     82
     83  usb2_vbus-supply:
     84    description: Regulator controlling USB2 Host controller
     85
     86  usb3_vbus-supply:
     87    description: Regulator controlling USB3 Host controller
     88
     89required:
     90  - "#phy-cells"
     91  - compatible
     92  - clocks
     93  - clock-names
     94  - reg
     95  - reg-names
     96  - resets
     97  - reset-names
     98
     99additionalProperties: false
    100
    101examples:
    102  - |
    103    #include <dt-bindings/gpio/gpio.h>
    104    #include <dt-bindings/clock/sun8i-h3-ccu.h>
    105    #include <dt-bindings/reset/sun8i-h3-ccu.h>
    106
    107    phy@1c19400 {
    108        #phy-cells = <1>;
    109        compatible = "allwinner,sun8i-h3-usb-phy";
    110        reg = <0x01c19400 0x2c>,
    111              <0x01c1a800 0x4>,
    112              <0x01c1b800 0x4>,
    113              <0x01c1c800 0x4>,
    114              <0x01c1d800 0x4>;
    115        reg-names = "phy_ctrl",
    116                    "pmu0",
    117                    "pmu1",
    118                    "pmu2",
    119                    "pmu3";
    120        clocks = <&ccu CLK_USB_PHY0>,
    121                 <&ccu CLK_USB_PHY1>,
    122                 <&ccu CLK_USB_PHY2>,
    123                 <&ccu CLK_USB_PHY3>;
    124        clock-names = "usb0_phy",
    125                      "usb1_phy",
    126                      "usb2_phy",
    127                      "usb3_phy";
    128        resets = <&ccu RST_USB_PHY0>,
    129                 <&ccu RST_USB_PHY1>,
    130                 <&ccu RST_USB_PHY2>,
    131                 <&ccu RST_USB_PHY3>;
    132        reset-names = "usb0_reset",
    133                      "usb1_reset",
    134                      "usb2_reset",
    135                      "usb3_reset";
    136        usb0_id_det-gpios = <&pio 6 12 GPIO_ACTIVE_HIGH>; /* PG12 */
    137        usb0_vbus-supply = <&reg_usb0_vbus>;
    138        usb1_vbus-supply = <&reg_usb1_vbus>;
    139        usb2_vbus-supply = <&reg_usb2_vbus>;
    140        usb3_vbus-supply = <&reg_usb3_vbus>;
    141    };