cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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allwinner,sun9i-a80-usb-phy.yaml (2678B)

      1# SPDX-License-Identifier: GPL-2.0
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Allwinner A80 USB PHY Device Tree Bindings
      8
      9maintainers:
     10  - Chen-Yu Tsai <wens@csie.org>
     11  - Maxime Ripard <mripard@kernel.org>
     12
     13properties:
     14  "#phy-cells":
     15    const: 0
     16
     17  compatible:
     18    const: allwinner,sun9i-a80-usb-phy
     19
     20  reg:
     21    maxItems: 1
     22
     23  clocks:
     24    anyOf:
     25      - maxItems: 1
     26        description: Main PHY Clock
     27
     28      - items:
     29          - description: Main PHY clock
     30          - description: HSIC 12MHz clock
     31          - description: HSIC 480MHz clock
     32
     33  clock-names:
     34    oneOf:
     35      - const: phy
     36
     37      - items:
     38          - const: phy
     39          - const: hsic_12M
     40          - const: hsic_480M
     41
     42  resets:
     43    minItems: 1
     44    items:
     45      - description: Normal USB PHY reset
     46      - description: HSIC Reset
     47
     48  reset-names:
     49    minItems: 1
     50    items:
     51      - const: phy
     52      - const: hsic
     53
     54  phy_type:
     55    const: hsic
     56    description:
     57      When absent, the PHY type will be assumed to be normal USB.
     58
     59  phy-supply:
     60    description:
     61      Regulator that powers VBUS
     62
     63required:
     64  - "#phy-cells"
     65  - compatible
     66  - reg
     67  - clocks
     68  - clock-names
     69  - resets
     70  - reset-names
     71
     72additionalProperties: false
     73
     74if:
     75  properties:
     76    phy_type:
     77      const: hsic
     78
     79  required:
     80    - phy_type
     81
     82then:
     83  properties:
     84    clocks:
     85      maxItems: 3
     86
     87    clock-names:
     88      maxItems: 3
     89
     90    resets:
     91      maxItems: 2
     92
     93    reset-names:
     94      maxItems: 2
     95
     96examples:
     97  - |
     98    #include <dt-bindings/clock/sun9i-a80-usb.h>
     99    #include <dt-bindings/reset/sun9i-a80-usb.h>
    100
    101    usbphy1: phy@a00800 {
    102        compatible = "allwinner,sun9i-a80-usb-phy";
    103        reg = <0x00a00800 0x4>;
    104        clocks = <&usb_clocks CLK_USB0_PHY>;
    105        clock-names = "phy";
    106        resets = <&usb_clocks RST_USB0_PHY>;
    107        reset-names = "phy";
    108        phy-supply = <&reg_usb1_vbus>;
    109        #phy-cells = <0>;
    110    };
    111
    112  - |
    113    #include <dt-bindings/clock/sun9i-a80-usb.h>
    114    #include <dt-bindings/reset/sun9i-a80-usb.h>
    115
    116    usbphy3: phy@a02800 {
    117        compatible = "allwinner,sun9i-a80-usb-phy";
    118        reg = <0x00a02800 0x4>;
    119        clocks = <&usb_clocks CLK_USB2_PHY>,
    120                 <&usb_clocks CLK_USB_HSIC>,
    121                 <&usb_clocks CLK_USB2_HSIC>;
    122        clock-names = "phy",
    123                      "hsic_12M",
    124                      "hsic_480M";
    125        resets = <&usb_clocks RST_USB2_PHY>,
    126                 <&usb_clocks RST_USB2_HSIC>;
    127        reset-names = "phy",
    128                      "hsic";
    129        phy_type = "hsic";
    130        phy-supply = <&reg_usb3_vbus>;
    131        #phy-cells = <0>;
    132    };