cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,sr-pcie-phy.txt (961B)


      1Broadcom Stingray PCIe PHY
      2
      3Required properties:
      4- compatible: must be "brcm,sr-pcie-phy"
      5- reg: base address and length of the PCIe SS register space
      6- brcm,sr-cdru: phandle to the CDRU syscon node
      7- brcm,sr-mhb: phandle to the MHB syscon node
      8- #phy-cells: Must be 1, denotes the PHY index
      9
     10For PAXB based root complex, one can have a configuration of up to 8 PHYs
     11PHY index goes from 0 to 7
     12
     13For the internal PAXC based root complex, PHY index is always 8
     14
     15Example:
     16	mhb: syscon@60401000 {
     17		compatible = "brcm,sr-mhb", "syscon";
     18		reg = <0 0x60401000 0 0x38c>;
     19	};
     20
     21	cdru: syscon@6641d000 {
     22		compatible = "brcm,sr-cdru", "syscon";
     23		reg = <0 0x6641d000 0 0x400>;
     24	};
     25
     26	pcie_phy: phy@40000000 {
     27		compatible = "brcm,sr-pcie-phy";
     28		reg = <0 0x40000000 0 0x800>;
     29		brcm,sr-cdru = <&cdru>;
     30		brcm,sr-mhb = <&mhb>;
     31		#phy-cells = <1>;
     32	};
     33
     34	/* users of the PCIe PHY */
     35
     36	pcie0: pcie@48000000 {
     37		...
     38		...
     39		phys = <&pcie_phy 0>;
     40		phy-names = "pcie-phy";
     41	};