cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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fsl,imx8-pcie-phy.yaml (2376B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Freescale i.MX8 SoC series PCIe PHY Device Tree Bindings
      8
      9maintainers:
     10  - Richard Zhu <hongxing.zhu@nxp.com>
     11
     12properties:
     13  "#phy-cells":
     14    const: 0
     15
     16  compatible:
     17    enum:
     18      - fsl,imx8mm-pcie-phy
     19
     20  reg:
     21    maxItems: 1
     22
     23  clocks:
     24    maxItems: 1
     25
     26  clock-names:
     27    items:
     28      - const: ref
     29
     30  resets:
     31    maxItems: 1
     32
     33  reset-names:
     34    items:
     35      - const: pciephy
     36
     37  fsl,refclk-pad-mode:
     38    description: |
     39      Specifies the mode of the refclk pad used. It can be UNUSED(PHY
     40      refclock is derived from SoC internal source), INPUT(PHY refclock
     41      is provided externally via the refclk pad) or OUTPUT(PHY refclock
     42      is derived from SoC internal source and provided on the refclk pad).
     43      Refer include/dt-bindings/phy/phy-imx8-pcie.h for the constants
     44      to be used.
     45    $ref: /schemas/types.yaml#/definitions/uint32
     46    enum: [ 0, 1, 2 ]
     47
     48  fsl,tx-deemph-gen1:
     49    description: Gen1 De-emphasis value (optional).
     50    $ref: /schemas/types.yaml#/definitions/uint32
     51    default: 0
     52
     53  fsl,tx-deemph-gen2:
     54    description: Gen2 De-emphasis value (optional).
     55    $ref: /schemas/types.yaml#/definitions/uint32
     56    default: 0
     57
     58  fsl,clkreq-unsupported:
     59    type: boolean
     60    description: A boolean property indicating the CLKREQ# signal is
     61      not supported in the board design (optional)
     62
     63required:
     64  - "#phy-cells"
     65  - compatible
     66  - reg
     67  - clocks
     68  - clock-names
     69  - fsl,refclk-pad-mode
     70
     71additionalProperties: false
     72
     73examples:
     74  - |
     75    #include <dt-bindings/clock/imx8mm-clock.h>
     76    #include <dt-bindings/phy/phy-imx8-pcie.h>
     77    #include <dt-bindings/reset/imx8mq-reset.h>
     78
     79    pcie_phy: pcie-phy@32f00000 {
     80            compatible = "fsl,imx8mm-pcie-phy";
     81            reg = <0x32f00000 0x10000>;
     82            clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
     83            clock-names = "ref";
     84            assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
     85            assigned-clock-rates = <100000000>;
     86            assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
     87            resets = <&src IMX8MQ_RESET_PCIEPHY>;
     88            reset-names = "pciephy";
     89            fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
     90            #phy-cells = <0>;
     91    };
     92...