cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel,lgm-emmc-phy.yaml (1609B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings
      8
      9maintainers:
     10  - Ramuthevar Vadivel Murugan <vadivel.muruganx.ramuthevar@linux.intel.com>
     11
     12description: |+
     13  Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
     14  node is used to reference the base address of eMMC phy registers.
     15
     16  The eMMC PHY node should be the child of a syscon node with the
     17  required property:
     18
     19  - compatible:         Should be one of the following:
     20                        "intel,lgm-syscon", "syscon"
     21  - reg:
     22      maxItems: 1
     23
     24properties:
     25  compatible:
     26    enum:
     27      - intel,lgm-emmc-phy
     28      - intel,keembay-emmc-phy
     29
     30  "#phy-cells":
     31    const: 0
     32
     33  reg:
     34    maxItems: 1
     35
     36  clocks:
     37    maxItems: 1
     38
     39  clock-names:
     40    items:
     41      - const: emmcclk
     42
     43required:
     44  - "#phy-cells"
     45  - compatible
     46  - reg
     47  - clocks
     48
     49additionalProperties: false
     50
     51examples:
     52  - |
     53    sysconf: chiptop@e0200000 {
     54      compatible = "intel,lgm-syscon", "syscon";
     55      reg = <0xe0200000 0x100>;
     56      #address-cells = <1>;
     57      #size-cells = <1>;
     58
     59      emmc_phy: emmc-phy@a8 {
     60        compatible = "intel,lgm-emmc-phy";
     61        reg = <0x00a8 0x10>;
     62        clocks = <&emmc>;
     63        #phy-cells = <0>;
     64      };
     65    };
     66
     67  - |
     68    phy@20290000 {
     69          compatible = "intel,keembay-emmc-phy";
     70          reg = <0x20290000 0x54>;
     71          clocks = <&emmc>;
     72          clock-names = "emmcclk";
     73          #phy-cells = <0>;
     74    };
     75...