cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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intel,lgm-usb-phy.yaml (1151B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/intel,lgm-usb-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Intel LGM USB PHY Device Tree Bindings
      8
      9maintainers:
     10  - Vadivel Murugan Ramuthevar <vadivel.muruganx.ramuthevar@linux.intel.com>
     11
     12properties:
     13  compatible:
     14    const: intel,lgm-usb-phy
     15
     16  reg:
     17    maxItems: 1
     18
     19  clocks:
     20    maxItems: 1
     21
     22  resets:
     23    items:
     24      - description: USB PHY and Host controller reset
     25      - description: APB BUS reset
     26      - description: General Hardware reset
     27
     28  reset-names:
     29    items:
     30      - const: phy
     31      - const: apb
     32      - const: phy31
     33
     34  "#phy-cells":
     35    const: 0
     36
     37required:
     38  - compatible
     39  - clocks
     40  - reg
     41  - resets
     42  - reset-names
     43  - "#phy-cells"
     44
     45additionalProperties: false
     46
     47examples:
     48  - |
     49    usb-phy@e7e00000 {
     50        compatible = "intel,lgm-usb-phy";
     51        reg = <0xe7e00000 0x10000>;
     52        clocks = <&cgu0 153>;
     53        resets = <&rcu 0x70 0x24>,
     54                 <&rcu 0x70 0x26>,
     55                 <&rcu 0x70 0x28>;
     56        reset-names = "phy", "apb", "phy31";
     57        #phy-cells = <0>;
     58    };