cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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marvell,armada-cp110-utmi-phy.yaml (2411B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2
      3%YAML 1.2
      4---
      5$id: "http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#"
      6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      7
      8title: Marvell Armada CP110/CP115 UTMI PHY
      9
     10maintainers:
     11  - Konstantin Porotchkin <kostap@marvell.com>
     12
     13description:
     14  On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
     15  Each of two exiting UTMI PHYs could be connected to either USB host or USB device
     16  controller.
     17  The USB device controller can only be connected to a single UTMI PHY port
     18                      0.H----- USB HOST0
     19  UTMI PHY0  --------/
     20                      0.D-----0
     21                               \------ USB DEVICE
     22                      1.D-----1
     23  UTMI PHY1  --------\
     24                      1.H----- USB HOST1
     25
     26properties:
     27  compatible:
     28    const: marvell,cp110-utmi-phy
     29
     30  reg:
     31    maxItems: 1
     32
     33  "#address-cells":
     34    const: 1
     35
     36  "#size-cells":
     37    const: 0
     38
     39  marvell,system-controller:
     40    description:
     41      Phandle to the system controller node
     42    $ref: /schemas/types.yaml#/definitions/phandle
     43
     44#Required child nodes:
     45
     46patternProperties:
     47  "^usb-phy@[0|1]$":
     48    type: object
     49    description:
     50      Each UTMI PHY port must be represented as a sub-node.
     51
     52    properties:
     53      reg:
     54        description: phy port index.
     55        maxItems: 1
     56
     57      "#phy-cells":
     58        const: 0
     59
     60    required:
     61      - reg
     62      - "#phy-cells"
     63
     64    additionalProperties: false
     65
     66required:
     67  - compatible
     68  - reg
     69  - "#address-cells"
     70  - "#size-cells"
     71  - marvell,system-controller
     72
     73additionalProperties: false
     74
     75examples:
     76  - |
     77    cp0_utmi: utmi@580000 {
     78      compatible = "marvell,cp110-utmi-phy";
     79      reg = <0x580000 0x2000>;
     80      marvell,system-controller = <&cp0_syscon0>;
     81      #address-cells = <1>;
     82      #size-cells = <0>;
     83
     84      cp0_utmi0: usb-phy@0 {
     85        reg = <0>;
     86        #phy-cells = <0>;
     87      };
     88
     89      cp0_utmi1: usb-phy@1 {
     90        reg = <1>;
     91        #phy-cells = <0>;
     92      };
     93    };
     94
     95    cp0_usb3_0 {
     96      usb-phy = <&cp0_usb3_0_phy0>;
     97      phys = <&cp0_utmi0>;
     98      phy-names = "utmi";
     99      /* UTMI0 is connected to USB host controller (default mode) */
    100      dr_mode = "host";
    101    };
    102
    103    cp0_usb3_1 {
    104      usb-phy = <&cp0_usb3_0_phy1>;
    105      phys = <&cp0_utmi1>;
    106      phy-names = "utmi";
    107      /* UTMI1 is connected to USB device controller */
    108      dr_mode = "peripheral";
    109    };