mediatek,tphy.yaml (8794B)
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2# Copyright (c) 2020 MediaTek 3%YAML 1.2 4--- 5$id: http://devicetree.org/schemas/phy/mediatek,tphy.yaml# 6$schema: http://devicetree.org/meta-schemas/core.yaml# 7 8title: MediaTek T-PHY Controller Device Tree Bindings 9 10maintainers: 11 - Chunfeng Yun <chunfeng.yun@mediatek.com> 12 13description: | 14 The T-PHY controller supports physical layer functionality for a number of 15 controllers on MediaTek SoCs, includes USB2.0, USB3.0, PCIe and SATA. 16 17 Layout differences of banks between T-PHY V1 (mt8173/mt2701) and 18 T-PHY V2 (mt2712) / V3 (mt8195) when works on USB mode: 19 ----------------------------------- 20 Version 1: 21 port offset bank 22 shared 0x0000 SPLLC 23 0x0100 FMREG 24 u2 port0 0x0800 U2PHY_COM 25 u3 port0 0x0900 U3PHYD 26 0x0a00 U3PHYD_BANK2 27 0x0b00 U3PHYA 28 0x0c00 U3PHYA_DA 29 u2 port1 0x1000 U2PHY_COM 30 u3 port1 0x1100 U3PHYD 31 0x1200 U3PHYD_BANK2 32 0x1300 U3PHYA 33 0x1400 U3PHYA_DA 34 u2 port2 0x1800 U2PHY_COM 35 ... 36 37 Version 2/3: 38 port offset bank 39 u2 port0 0x0000 MISC 40 0x0100 FMREG 41 0x0300 U2PHY_COM 42 u3 port0 0x0700 SPLLC 43 0x0800 CHIP 44 0x0900 U3PHYD 45 0x0a00 U3PHYD_BANK2 46 0x0b00 U3PHYA 47 0x0c00 U3PHYA_DA 48 u2 port1 0x1000 MISC 49 0x1100 FMREG 50 0x1300 U2PHY_COM 51 u3 port1 0x1700 SPLLC 52 0x1800 CHIP 53 0x1900 U3PHYD 54 0x1a00 U3PHYD_BANK2 55 0x1b00 U3PHYA 56 0x1c00 U3PHYA_DA 57 u2 port2 0x2000 MISC 58 ... 59 60 SPLLC shared by u3 ports and FMREG shared by u2 ports on V1 are put back 61 into each port; a new bank MISC for u2 ports and CHIP for u3 ports are 62 added on V2; the FMREG bank for slew rate calibration is not used anymore 63 and reserved on V3; 64 65properties: 66 $nodename: 67 pattern: "^t-phy@[0-9a-f]+$" 68 69 compatible: 70 oneOf: 71 - items: 72 - enum: 73 - mediatek,mt2701-tphy 74 - mediatek,mt7623-tphy 75 - mediatek,mt7622-tphy 76 - mediatek,mt8516-tphy 77 - const: mediatek,generic-tphy-v1 78 - items: 79 - enum: 80 - mediatek,mt2712-tphy 81 - mediatek,mt7629-tphy 82 - mediatek,mt8183-tphy 83 - mediatek,mt8186-tphy 84 - mediatek,mt8192-tphy 85 - const: mediatek,generic-tphy-v2 86 - items: 87 - enum: 88 - mediatek,mt8195-tphy 89 - const: mediatek,generic-tphy-v3 90 - const: mediatek,mt2701-u3phy 91 deprecated: true 92 - const: mediatek,mt2712-u3phy 93 deprecated: true 94 - const: mediatek,mt8173-u3phy 95 96 reg: 97 description: 98 Register shared by multiple ports, exclude port's private register. 99 It is needed for T-PHY V1, such as mt2701 and mt8173, but not for 100 T-PHY V2/V3, such as mt2712. 101 maxItems: 1 102 103 "#address-cells": 104 enum: [1, 2] 105 106 "#size-cells": 107 enum: [1, 2] 108 109 # Used with non-empty value if optional 'reg' is not provided. 110 # The format of the value is an arbitrary number of triplets of 111 # (child-bus-address, parent-bus-address, length). 112 ranges: true 113 114 mediatek,src-ref-clk-mhz: 115 description: 116 Frequency of reference clock for slew rate calibrate 117 default: 26 118 119 mediatek,src-coef: 120 description: 121 Coefficient for slew rate calibrate, depends on SoC process 122 $ref: /schemas/types.yaml#/definitions/uint32 123 default: 28 124 125# Required child node: 126patternProperties: 127 "^(usb|pcie|sata)-phy@[0-9a-f]+$": 128 type: object 129 description: 130 A sub-node is required for each port the controller provides. 131 Address range information including the usual 'reg' property 132 is used inside these nodes to describe the controller's topology. 133 134 properties: 135 reg: 136 maxItems: 1 137 138 clocks: 139 minItems: 1 140 items: 141 - description: Reference clock, (HS is 48Mhz, SS/P is 24~27Mhz) 142 - description: Reference clock of analog phy 143 description: 144 Uses both clocks if the clock of analog and digital phys are 145 separated, otherwise uses "ref" clock only if needed. 146 147 clock-names: 148 minItems: 1 149 items: 150 - const: ref 151 - const: da_ref 152 153 "#phy-cells": 154 const: 1 155 description: | 156 The cells contain the following arguments. 157 158 - description: The PHY type 159 enum: 160 - PHY_TYPE_USB2 161 - PHY_TYPE_USB3 162 - PHY_TYPE_PCIE 163 - PHY_TYPE_SATA 164 165 nvmem-cells: 166 items: 167 - description: internal R efuse for U2 PHY or U3/PCIe PHY 168 - description: rx_imp_sel efuse for U3/PCIe PHY 169 - description: tx_imp_sel efuse for U3/PCIe PHY 170 description: | 171 Phandles to nvmem cell that contains the efuse data; 172 Available only for U2 PHY or U3/PCIe PHY of version 2/3, these 173 three items should be provided at the same time for U3/PCIe PHY, 174 when use software to load efuse; 175 If unspecified, will use hardware auto-load efuse. 176 177 nvmem-cell-names: 178 items: 179 - const: intr 180 - const: rx_imp 181 - const: tx_imp 182 183 # The following optional vendor properties are only for debug or HQA test 184 mediatek,eye-src: 185 description: 186 The value of slew rate calibrate (U2 phy) 187 $ref: /schemas/types.yaml#/definitions/uint32 188 minimum: 1 189 maximum: 7 190 191 mediatek,eye-vrt: 192 description: 193 The selection of VRT reference voltage (U2 phy) 194 $ref: /schemas/types.yaml#/definitions/uint32 195 minimum: 1 196 maximum: 7 197 198 mediatek,eye-term: 199 description: 200 The selection of HS_TX TERM reference voltage (U2 phy) 201 $ref: /schemas/types.yaml#/definitions/uint32 202 minimum: 1 203 maximum: 7 204 205 mediatek,intr: 206 description: 207 The selection of internal resistor (U2 phy) 208 $ref: /schemas/types.yaml#/definitions/uint32 209 minimum: 1 210 maximum: 31 211 212 mediatek,discth: 213 description: 214 The selection of disconnect threshold (U2 phy) 215 $ref: /schemas/types.yaml#/definitions/uint32 216 minimum: 1 217 maximum: 15 218 219 mediatek,bc12: 220 description: 221 Specify the flag to enable BC1.2 if support it 222 type: boolean 223 224 mediatek,syscon-type: 225 $ref: /schemas/types.yaml#/definitions/phandle-array 226 maxItems: 1 227 description: 228 A phandle to syscon used to access the register of type switch, 229 the field should always be 3 cells long. 230 items: 231 items: 232 - description: 233 The first cell represents a phandle to syscon 234 - description: 235 The second cell represents the register offset 236 - description: 237 The third cell represents the index of config segment 238 enum: [0, 1, 2, 3] 239 240 required: 241 - reg 242 - "#phy-cells" 243 244 additionalProperties: false 245 246required: 247 - compatible 248 - "#address-cells" 249 - "#size-cells" 250 - ranges 251 252additionalProperties: false 253 254examples: 255 - | 256 #include <dt-bindings/clock/mt8173-clk.h> 257 #include <dt-bindings/interrupt-controller/arm-gic.h> 258 #include <dt-bindings/interrupt-controller/irq.h> 259 #include <dt-bindings/phy/phy.h> 260 usb@11271000 { 261 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 262 reg = <0x11271000 0x3000>, <0x11280700 0x0100>; 263 reg-names = "mac", "ippc"; 264 phys = <&u2port0 PHY_TYPE_USB2>, 265 <&u3port0 PHY_TYPE_USB3>, 266 <&u2port1 PHY_TYPE_USB2>; 267 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 268 clocks = <&topckgen CLK_TOP_USB30_SEL>; 269 clock-names = "sys_ck"; 270 }; 271 272 t-phy@11290000 { 273 compatible = "mediatek,mt8173-u3phy"; 274 reg = <0x11290000 0x800>; 275 #address-cells = <1>; 276 #size-cells = <1>; 277 ranges; 278 279 u2port0: usb-phy@11290800 { 280 reg = <0x11290800 0x100>; 281 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>, <&clk48m>; 282 clock-names = "ref", "da_ref"; 283 #phy-cells = <1>; 284 }; 285 286 u3port0: usb-phy@11290900 { 287 reg = <0x11290900 0x700>; 288 clocks = <&clk26m>; 289 clock-names = "ref"; 290 #phy-cells = <1>; 291 }; 292 293 u2port1: usb-phy@11291000 { 294 reg = <0x11291000 0x100>; 295 #phy-cells = <1>; 296 }; 297 }; 298 299...