cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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phy-cadence-sierra.yaml (4391B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Cadence Sierra PHY binding
      8
      9description:
     10  This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
     11  multiprotocol combinations including protocols such as PCIe, USB etc.
     12
     13maintainers:
     14  - Swapnil Jakhade <sjakhade@cadence.com>
     15  - Yuti Amonkar <yamonkar@cadence.com>
     16
     17properties:
     18  compatible:
     19    enum:
     20      - cdns,sierra-phy-t0
     21      - ti,sierra-phy-t0
     22
     23  '#address-cells':
     24    const: 1
     25
     26  '#size-cells':
     27    const: 0
     28
     29  '#clock-cells':
     30    const: 1
     31
     32  resets:
     33    minItems: 1
     34    items:
     35      - description: Sierra PHY reset.
     36      - description: Sierra APB reset. This is optional.
     37
     38  reset-names:
     39    minItems: 1
     40    items:
     41      - const: sierra_reset
     42      - const: sierra_apb
     43
     44  reg:
     45    maxItems: 1
     46    description:
     47      Offset of the Sierra PHY configuration registers.
     48
     49  reg-names:
     50    const: serdes
     51
     52  clocks:
     53    minItems: 2
     54    maxItems: 4
     55
     56  clock-names:
     57    minItems: 2
     58    items:
     59      - const: cmn_refclk_dig_div
     60      - const: cmn_refclk1_dig_div
     61      - const: pll0_refclk
     62      - const: pll1_refclk
     63
     64  assigned-clocks:
     65    minItems: 1
     66    maxItems: 2
     67
     68  assigned-clock-parents:
     69    minItems: 1
     70    maxItems: 2
     71
     72  cdns,autoconf:
     73    type: boolean
     74    description:
     75      A boolean property whose presence indicates that the PHY registers will be
     76      configured by hardware. If not present, all sub-node optional properties
     77      must be provided.
     78
     79patternProperties:
     80  '^phy@[0-9a-f]$':
     81    type: object
     82    description:
     83      Each group of PHY lanes with a single master lane should be represented as
     84      a sub-node. Note that the actual configuration of each lane is determined
     85      by hardware strapping, and must match the configuration specified here.
     86    properties:
     87      reg:
     88        description:
     89          The master lane number. This is the lowest numbered lane in the lane group.
     90        minimum: 0
     91        maximum: 15
     92
     93      resets:
     94        minItems: 1
     95        maxItems: 4
     96        description:
     97          Contains list of resets, one per lane, to get all the link lanes out of reset.
     98
     99      "#phy-cells":
    100        const: 0
    101
    102      cdns,phy-type:
    103        description:
    104          Specifies the type of PHY for which the group of PHY lanes is used.
    105          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
    106        $ref: /schemas/types.yaml#/definitions/uint32
    107        enum: [2, 4]
    108
    109      cdns,num-lanes:
    110        description:
    111          Number of lanes in this group. The group is made up of consecutive lanes.
    112        $ref: /schemas/types.yaml#/definitions/uint32
    113        minimum: 1
    114        maximum: 16
    115
    116      cdns,ssc-mode:
    117        description:
    118          Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
    119          EXTERNAL_SSC or INTERNAL_SSC.
    120          Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
    121        $ref: /schemas/types.yaml#/definitions/uint32
    122        enum: [0, 1, 2]
    123        default: 1
    124
    125    required:
    126      - reg
    127      - resets
    128      - "#phy-cells"
    129
    130    additionalProperties: false
    131
    132required:
    133  - compatible
    134  - "#address-cells"
    135  - "#size-cells"
    136  - reg
    137  - resets
    138  - reset-names
    139
    140additionalProperties: false
    141
    142examples:
    143  - |
    144    #include <dt-bindings/phy/phy.h>
    145
    146    bus {
    147        #address-cells = <2>;
    148        #size-cells = <2>;
    149
    150        sierra-phy@fd240000 {
    151            compatible = "cdns,sierra-phy-t0";
    152            reg = <0x0 0xfd240000 0x0 0x40000>;
    153            resets = <&phyrst 0>, <&phyrst 1>;
    154            reset-names = "sierra_reset", "sierra_apb";
    155            clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
    156            clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
    157            #address-cells = <1>;
    158            #size-cells = <0>;
    159            pcie0_phy0: phy@0 {
    160                reg = <0>;
    161                resets = <&phyrst 2>;
    162                cdns,num-lanes = <2>;
    163                #phy-cells = <0>;
    164                cdns,phy-type = <PHY_TYPE_PCIE>;
    165            };
    166            pcie0_phy1: phy@2 {
    167                reg = <2>;
    168                resets = <&phyrst 4>;
    169                cdns,num-lanes = <1>;
    170                #phy-cells = <0>;
    171                cdns,phy-type = <PHY_TYPE_PCIE>;
    172            };
    173        };
    174    };