phy-ocelot-serdes.txt (1364B)
1Microsemi Ocelot SerDes muxing driver 2------------------------------------- 3 4On Microsemi Ocelot, there is a handful of registers in HSIO address 5space for setting up the SerDes to switch port muxing. 6 7A SerDes X can be "muxed" to work with switch port Y or Z for example. 8One specific SerDes can also be used as a PCIe interface. 9 10Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one. 11 12There are two kinds of SerDes: SERDES1G supports 10/100Mbps in 13half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports 1410/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode. 15 16Also, SERDES6G number (aka "macro") 0 is the only interface supporting 17QSGMII. 18 19This is a child of the HSIO syscon ("mscc,ocelot-hsio", see 20Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot. 21 22Required properties: 23 24- compatible: should be "mscc,vsc7514-serdes" 25- #phy-cells : from the generic phy bindings, must be 2. 26 The first number defines the input port to use for a given 27 SerDes macro. The second defines the macro to use. They are 28 defined in dt-bindings/phy/phy-ocelot-serdes.h 29 30Example: 31 32 serdes: serdes { 33 compatible = "mscc,vsc7514-serdes"; 34 #phy-cells = <2>; 35 }; 36 37 ethernet { 38 port1 { 39 phy-handle = <&phy_foo>; 40 /* Link SERDES1G_5 to port1 */ 41 phys = <&serdes 1 SERDES1G_5>; 42 }; 43 };