cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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phy-tegra194-p2u.yaml (1081B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: NVIDIA Tegra194 P2U binding
      8
      9maintainers:
     10  - Thierry Reding <treding@nvidia.com>
     11
     12description: >
     13  Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
     14  Speed) each interfacing with 12 and 8 P2U instances respectively.
     15  A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
     16  interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
     17  lane.
     18
     19properties:
     20  compatible:
     21    const: nvidia,tegra194-p2u
     22
     23  reg:
     24    maxItems: 1
     25    description: Should be the physical address space and length of respective each P2U instance.
     26
     27  reg-names:
     28    items:
     29      - const: ctl
     30
     31  '#phy-cells':
     32    const: 0
     33
     34additionalProperties: false
     35
     36examples:
     37  - |
     38    p2u_hsio_0: phy@3e10000 {
     39        compatible = "nvidia,tegra194-p2u";
     40        reg = <0x03e10000 0x10000>;
     41        reg-names = "ctl";
     42
     43        #phy-cells = <0>;
     44    };