cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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qcom,usb-ss.yaml (1798B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: "http://devicetree.org/schemas/phy/qcom,usb-ss.yaml#"
      5$schema: "http://devicetree.org/meta-schemas/core.yaml#"
      6
      7title: Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
      8
      9maintainers:
     10  - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
     11
     12description: |
     13  Qualcomm Synopsys 1.0.0 SuperSpeed USB PHY
     14
     15properties:
     16  compatible:
     17    enum:
     18      - qcom,usb-ss-28nm-phy
     19
     20  reg:
     21    maxItems: 1
     22
     23  "#phy-cells":
     24    const: 0
     25
     26  clocks:
     27    items:
     28      - description: rpmcc clock
     29      - description: PHY AHB clock
     30      - description: SuperSpeed pipe clock
     31
     32  clock-names:
     33    items:
     34      - const: ref
     35      - const: ahb
     36      - const: pipe
     37
     38  vdd-supply:
     39    description: phandle to the regulator VDD supply node.
     40
     41  vdda1p8-supply:
     42    description: phandle to the regulator 1.8V supply node.
     43
     44  resets:
     45    items:
     46      - description: COM reset
     47      - description: PHY reset line
     48
     49  reset-names:
     50    items:
     51      - const: com
     52      - const: phy
     53
     54required:
     55  - compatible
     56  - reg
     57  - "#phy-cells"
     58  - clocks
     59  - clock-names
     60  - vdd-supply
     61  - vdda1p8-supply
     62
     63additionalProperties: false
     64
     65examples:
     66  - |
     67    #include <dt-bindings/clock/qcom,gcc-qcs404.h>
     68    #include <dt-bindings/clock/qcom,rpmcc.h>
     69    usb3_phy: usb3-phy@78000 {
     70        compatible = "qcom,usb-ss-28nm-phy";
     71        reg = <0x78000 0x400>;
     72        #phy-cells = <0>;
     73        clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
     74                 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
     75                 <&gcc GCC_USB3_PHY_PIPE_CLK>;
     76        clock-names = "ref", "ahb", "pipe";
     77        resets = <&gcc GCC_USB3_PHY_BCR>,
     78                 <&gcc GCC_USB3PHY_PHY_BCR>;
     79        reset-names = "com", "phy";
     80        vdd-supply = <&vreg_l3_1p05>;
     81        vdda1p8-supply = <&vreg_l5_1p8>;
     82    };
     83...