cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

rockchip,px30-dsi-dphy.yaml (1291B)

      1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Rockchip MIPI DPHY with additional LVDS/TTL modes
      8
      9maintainers:
     10  - Heiko Stuebner <heiko@sntech.de>
     11
     12properties:
     13  "#phy-cells":
     14    const: 0
     15
     16  compatible:
     17    enum:
     18      - rockchip,px30-dsi-dphy
     19      - rockchip,rk3128-dsi-dphy
     20      - rockchip,rk3368-dsi-dphy
     21
     22  reg:
     23    maxItems: 1
     24
     25  clocks:
     26    items:
     27      - description: PLL reference clock
     28      - description: Module clock
     29
     30  clock-names:
     31    items:
     32      - const: ref
     33      - const: pclk
     34
     35  power-domains:
     36    maxItems: 1
     37    description: phandle to the associated power domain
     38
     39  resets:
     40    items:
     41      - description: exclusive PHY reset line
     42
     43  reset-names:
     44    items:
     45      - const: apb
     46
     47required:
     48  - "#phy-cells"
     49  - compatible
     50  - reg
     51  - clocks
     52  - clock-names
     53  - resets
     54  - reset-names
     55
     56additionalProperties: false
     57
     58examples:
     59  - |
     60    dsi_dphy: phy@ff2e0000 {
     61        compatible = "rockchip,px30-dsi-dphy";
     62        reg = <0xff2e0000 0x10000>;
     63        clocks = <&pmucru 13>, <&cru 12>;
     64        clock-names = "ref", "pclk";
     65        resets = <&cru 12>;
     66        reset-names = "apb";
     67        #phy-cells = <0>;
     68    };
     69
     70...