cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

samsung,exynos-pcie-phy.yaml (1279B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/samsung,exynos-pcie-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung SoC series PCIe PHY Device Tree Bindings
      8
      9maintainers:
     10  - Marek Szyprowski <m.szyprowski@samsung.com>
     11  - Jaehoon Chung <jh80.chung@samsung.com>
     12
     13properties:
     14  "#phy-cells":
     15    const: 0
     16
     17  compatible:
     18    const: samsung,exynos5433-pcie-phy
     19
     20  reg:
     21    maxItems: 1
     22
     23  samsung,pmu-syscon:
     24    $ref: '/schemas/types.yaml#/definitions/phandle'
     25    description: phandle for PMU system controller interface, used to
     26                 control PMU registers bits for PCIe PHY
     27
     28  samsung,fsys-sysreg:
     29    $ref: '/schemas/types.yaml#/definitions/phandle'
     30    description: phandle for FSYS sysreg interface, used to control
     31                 sysreg registers bits for PCIe PHY
     32
     33required:
     34  - "#phy-cells"
     35  - compatible
     36  - reg
     37  - samsung,pmu-syscon
     38  - samsung,fsys-sysreg
     39
     40additionalProperties: false
     41
     42examples:
     43  - |
     44    pcie_phy: pcie-phy@15680000 {
     45        compatible = "samsung,exynos5433-pcie-phy";
     46        reg = <0x15680000 0x1000>;
     47        samsung,pmu-syscon = <&pmu_system_controller>;
     48        samsung,fsys-sysreg = <&syscon_fsys>;
     49        #phy-cells = <0>;
     50    };
     51...