cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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samsung,ufs-phy.yaml (1938B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Samsung SoC series UFS PHY Device Tree Bindings
      8
      9maintainers:
     10  - Alim Akhtar <alim.akhtar@samsung.com>
     11
     12properties:
     13  "#phy-cells":
     14    const: 0
     15
     16  compatible:
     17    enum:
     18      - samsung,exynos7-ufs-phy
     19      - samsung,exynosautov9-ufs-phy
     20
     21  reg:
     22    maxItems: 1
     23
     24  reg-names:
     25    items:
     26      - const: phy-pma
     27
     28  clocks:
     29    items:
     30      - description: PLL reference clock
     31      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
     32      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
     33      - description: symbol clock for output symbol ( tx0 symbol clock)
     34
     35  clock-names:
     36    items:
     37      - const: ref_clk
     38      - const: rx1_symbol_clk
     39      - const: rx0_symbol_clk
     40      - const: tx0_symbol_clk
     41
     42  samsung,pmu-syscon:
     43    $ref: '/schemas/types.yaml#/definitions/phandle'
     44    description: phandle for PMU system controller interface, used to
     45                 control pmu registers bits for ufs m-phy
     46
     47required:
     48  - "#phy-cells"
     49  - compatible
     50  - reg
     51  - reg-names
     52  - clocks
     53  - clock-names
     54  - samsung,pmu-syscon
     55
     56additionalProperties: false
     57
     58examples:
     59  - |
     60    #include <dt-bindings/clock/exynos7-clk.h>
     61
     62    ufs_phy: ufs-phy@15571800 {
     63        compatible = "samsung,exynos7-ufs-phy";
     64        reg = <0x15571800 0x240>;
     65        reg-names = "phy-pma";
     66        samsung,pmu-syscon = <&pmu_system_controller>;
     67        #phy-cells = <0>;
     68        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
     69                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
     70                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
     71                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
     72        clock-names = "ref_clk", "rx1_symbol_clk",
     73                      "rx0_symbol_clk", "tx0_symbol_clk";
     74
     75    };
     76...