cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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xlnx,zynqmp-psgtr.yaml (2410B)

      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
      8
      9maintainers:
     10  - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
     11
     12description: |
     13  This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
     14  GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
     15  Ethernet SGMII controllers.
     16
     17properties:
     18  "#phy-cells":
     19    const: 4
     20    description: |
     21      The cells contain the following arguments.
     22
     23      - description: The GTR lane
     24        minimum: 0
     25        maximum: 3
     26      - description: The PHY type
     27        enum:
     28          - PHY_TYPE_DP
     29          - PHY_TYPE_PCIE
     30          - PHY_TYPE_SATA
     31          - PHY_TYPE_SGMII
     32          - PHY_TYPE_USB3
     33      - description: The PHY instance
     34        minimum: 0
     35        maximum: 1 # for DP, SATA or USB
     36        maximum: 3 # for PCIE or SGMII
     37      - description: The reference clock number
     38        minimum: 0
     39        maximum: 3
     40
     41  compatible:
     42    enum:
     43      - xlnx,zynqmp-psgtr-v1.1
     44      - xlnx,zynqmp-psgtr
     45
     46  clocks:
     47    minItems: 1
     48    maxItems: 4
     49    description: |
     50      Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
     51      inputs shall not have an entry.
     52
     53  clock-names:
     54    minItems: 1
     55    maxItems: 4
     56    items:
     57      pattern: "^ref[0-3]$"
     58
     59  reg:
     60    items:
     61      - description: SERDES registers block
     62      - description: SIOU registers block
     63
     64  reg-names:
     65    items:
     66      - const: serdes
     67      - const: siou
     68
     69  xlnx,tx-termination-fix:
     70    description: |
     71      Include this for fixing functional issue with the TX termination
     72      resistance in GT, which can be out of spec for the XCZU9EG silicon
     73      version.
     74    type: boolean
     75
     76required:
     77  - "#phy-cells"
     78  - compatible
     79  - reg
     80  - reg-names
     81
     82if:
     83  properties:
     84    compatible:
     85      const: xlnx,zynqmp-psgtr-v1.1
     86
     87then:
     88  properties:
     89    xlnx,tx-termination-fix: false
     90
     91additionalProperties: false
     92
     93examples:
     94  - |
     95    phy: phy@fd400000 {
     96        compatible = "xlnx,zynqmp-psgtr-v1.1";
     97        reg = <0xfd400000 0x40000>,
     98              <0xfd3d0000 0x1000>;
     99        reg-names = "serdes", "siou";
    100        clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
    101        clock-names = "ref1", "ref2", "ref3";
    102        #phy-cells = <4>;
    103    };
    104
    105...