cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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actions,s500-pinctrl.yaml (9282B)


      1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/actions,s500-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Actions Semi S500 SoC pinmux & GPIO controller
      8
      9maintainers:
     10  - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
     11  - Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
     12
     13description: |
     14  Pinmux & GPIO controller manages pin multiplexing & configuration including
     15  GPIO function selection & GPIO attributes configuration. Please refer to
     16  pinctrl-bindings.txt in this directory for common binding part and usage.
     17
     18properties:
     19  compatible:
     20    const: actions,s500-pinctrl
     21
     22  reg:
     23    items:
     24      - description: GPIO Output + GPIO Input + GPIO Data
     25      - description: Multiplexing Control
     26      - description: PAD Pull Control + PAD Schmitt Trigger Enable + PAD Control
     27      - description: PAD Drive Capacity Select
     28    minItems: 1
     29
     30  clocks:
     31    maxItems: 1
     32
     33  gpio-controller: true
     34
     35  gpio-ranges:
     36    maxItems: 1
     37
     38  '#gpio-cells':
     39    description:
     40      Specifies the pin number and flags, as defined in
     41      include/dt-bindings/gpio/gpio.h
     42    const: 2
     43
     44  interrupt-controller: true
     45
     46  '#interrupt-cells':
     47    description:
     48      Specifies the pin number and flags, as defined in
     49      include/dt-bindings/interrupt-controller/irq.h
     50    const: 2
     51
     52  interrupts:
     53    description:
     54      One interrupt per each of the 5 GPIO ports supported by the controller,
     55      sorted by port number ascending order.
     56    minItems: 5
     57    maxItems: 5
     58
     59patternProperties:
     60  '-pins$':
     61    type: object
     62    patternProperties:
     63      '^(.*-)?pinmux$':
     64        type: object
     65        description:
     66          Pinctrl node's client devices specify pin muxes using subnodes,
     67          which in turn use the standard properties below.
     68        $ref: pinmux-node.yaml#
     69
     70        properties:
     71          groups:
     72            description:
     73              List of gpio pin groups affected by the functions specified in
     74              this subnode.
     75            items:
     76              oneOf:
     77                - enum: [lcd0_d18_mfp, rmii_crs_dv_mfp, rmii_txd0_mfp,
     78                         rmii_txd1_mfp, rmii_txen_mfp, rmii_rxen_mfp, rmii_rxd1_mfp,
     79                         rmii_rxd0_mfp, rmii_ref_clk_mfp, i2s_d0_mfp, i2s_pcm1_mfp,
     80                         i2s0_pcm0_mfp, i2s1_pcm0_mfp, i2s_d1_mfp, ks_in2_mfp,
     81                         ks_in1_mfp, ks_in0_mfp, ks_in3_mfp, ks_out0_mfp,
     82                         ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
     83                         dsi_dp2_mfp, lcd0_d17_mfp, dsi_dp3_mfp, dsi_dn3_mfp,
     84                         dsi_dp0_mfp, lvds_ee_pn_mfp, spi0_i2c_pcm_mfp,
     85                         spi0_i2s_pcm_mfp, dsi_dnp1_cp_mfp, lvds_e_pn_mfp,
     86                         dsi_dn2_mfp, uart2_rtsb_mfp, uart2_ctsb_mfp, uart3_rtsb_mfp,
     87                         uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp, sd0_d2_d3_mfp,
     88                         sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
     89                         uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp,
     90                         uart0_tx_mfp, i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp,
     91                         pcm1_in_mfp, pcm1_clk_mfp, pcm1_sync_mfp, pcm1_out_mfp,
     92                         dnand_data_wr_mfp, dnand_acle_ce0_mfp, nand_ceb2_mfp,
     93                         nand_ceb3_mfp]
     94            minItems: 1
     95            maxItems: 32
     96
     97          function:
     98            description:
     99              Specify the alternative function to be configured for the
    100              given gpio pin groups.
    101            enum: [nor, eth_rmii, eth_smii, spi0, spi1, spi2, spi3, sens0,
    102                   sens1, uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0,
    103                   i2s1, pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
    104                   p0, sd0, sd1, sd2, i2c0, i2c1, i2c3, dsi, lvds, usb30, clko_25m,
    105                   mipi_csi, nand, spdif, ts, lcd0]
    106
    107        required:
    108          - groups
    109          - function
    110
    111        additionalProperties: false
    112
    113      '^(.*-)?pinconf$':
    114        type: object
    115        description:
    116          Pinctrl node's client devices specify pin configurations using
    117          subnodes, which in turn use the standard properties below.
    118        $ref: pincfg-node.yaml#
    119
    120        properties:
    121          groups:
    122            description:
    123              List of gpio pin groups affected by the drive-strength property
    124              specified in this subnode.
    125            items:
    126              oneOf:
    127                - enum: [sirq_drv, rmii_txd01_txen_drv, rmii_rxer_drv,
    128                         rmii_crs_drv, rmii_rxd10_drv, rmii_ref_clk_drv,
    129                         smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv,
    130                         i2s13_drv, pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv,
    131                         lcd_dsi_drv, dsi_drv, sd0_d0_d3_drv, sd1_d0_d3_drv,
    132                         sd0_cmd_drv, sd0_clk_drv, sd1_cmd_drv, sd1_clk_drv,
    133                         spi0_all_drv, uart0_rx_drv, uart0_tx_drv, uart2_all_drv,
    134                         i2c0_all_drv, i2c12_all_drv, sens0_pclk_drv,
    135                         sens0_ckout_drv, uart3_all_drv]
    136            minItems: 1
    137            maxItems: 32
    138
    139          pins:
    140            description:
    141              List of gpio pins affected by the bias-pull-* and
    142              input-schmitt-* properties specified in this subnode.
    143            items:
    144              oneOf:
    145                - enum: [dnand_dqs, dnand_dqsn, eth_txd0, eth_txd1, eth_txen,
    146                         eth_rxer, eth_crs_dv, eth_rxd1, eth_rxd0, eth_ref_clk,
    147                         eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
    148                         i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1,
    149                         i2s_mclk1, ks_in0, ks_in1, ks_in2, ks_in3, ks_out0, ks_out1,
    150                         ks_out2, lvds_oep, lvds_oen, lvds_odp, lvds_odn, lvds_ocp,
    151                         lvds_ocn, lvds_obp, lvds_obn, lvds_oap, lvds_oan, lvds_eep,
    152                         lvds_een, lvds_edp, lvds_edn, lvds_ecp, lvds_ecn, lvds_ebp,
    153                         lvds_ebn, lvds_eap, lvds_ean, lcd0_d18, lcd0_d17, dsi_dp3,
    154                         dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn, dsi_dp0, dsi_dn0,
    155                         dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2, sd0_d3, sd1_d0,
    156                         sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk, sd1_cmd, sd1_clk,
    157                         spi0_sclk, spi0_ss, spi0_miso, spi0_mosi, uart0_rx,
    158                         uart0_tx, i2c0_sclk, i2c0_sdata, sensor0_pclk,
    159                         sensor0_ckout, dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1,
    160                         dnand_ceb2, dnand_ceb3, uart2_rx, uart2_tx, uart2_rtsb,
    161                         uart2_ctsb, uart3_rx, uart3_tx, uart3_rtsb, uart3_ctsb,
    162                         pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, i2c1_sclk,
    163                         i2c1_sdata, i2c2_sclk, i2c2_sdata, csi_dn0, csi_dp0,
    164                         csi_dn1, csi_dp1, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
    165                         csi_cn, csi_cp, dnand_d0, dnand_d1, dnand_d2, dnand_d3,
    166                         dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_rb, dnand_rdb,
    167                         dnand_rdbn, dnand_wrb, porb, clko_25m, bsel, pkg0, pkg1,
    168                         pkg2, pkg3]
    169            minItems: 1
    170            maxItems: 64
    171
    172          bias-pull-up: true
    173          bias-pull-down: true
    174
    175          drive-strength:
    176            description:
    177              Selects the drive strength for the specified pins, in mA.
    178            enum: [2, 4, 8, 12]
    179
    180          input-schmitt-enable: true
    181          input-schmitt-disable: true
    182
    183        additionalProperties: false
    184
    185    additionalProperties: false
    186
    187allOf:
    188  - $ref: "pinctrl.yaml#"
    189
    190required:
    191  - compatible
    192  - reg
    193  - clocks
    194  - gpio-controller
    195  - gpio-ranges
    196  - '#gpio-cells'
    197  - interrupt-controller
    198  - '#interrupt-cells'
    199  - interrupts
    200
    201additionalProperties: false
    202
    203examples:
    204  - |
    205    #include <dt-bindings/interrupt-controller/arm-gic.h>
    206    pinctrl: pinctrl@b01b0000 {
    207        compatible = "actions,s500-pinctrl";
    208        reg = <0xb01b0000 0x40>, <0xb01b0040 0x10>,
    209              <0xb01b0060 0x18>, <0xb01b0080 0xc>;
    210        clocks = <&cmu 55>;
    211        gpio-controller;
    212        gpio-ranges = <&pinctrl 0 0 132>;
    213        #gpio-cells = <2>;
    214        interrupt-controller;
    215        #interrupt-cells = <2>;
    216        interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
    217                     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
    218                     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
    219                     <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
    220                     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
    221
    222        mmc0_pins: mmc0-pins {
    223            pinmux {
    224                groups = "sd0_d0_mfp", "sd0_d1_mfp", "sd0_d2_d3_mfp",
    225                         "sd0_cmd_mfp", "sd0_clk_mfp";
    226                function = "sd0";
    227            };
    228
    229            drv-pinconf {
    230                groups = "sd0_d0_d3_drv", "sd0_cmd_drv", "sd0_clk_drv";
    231                drive-strength = <8>;
    232            };
    233
    234            bias-pinconf {
    235                pins = "sd0_d0", "sd0_d1", "sd0_d2",
    236                       "sd0_d3", "sd0_cmd";
    237                bias-pull-up;
    238            };
    239        };
    240    };
    241
    242...