cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,bcm63268-pinctrl.yaml (4280B)

      1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
      2%YAML 1.2
      3---
      4$id: http://devicetree.org/schemas/pinctrl/brcm,bcm63268-pinctrl.yaml#
      5$schema: http://devicetree.org/meta-schemas/core.yaml#
      6
      7title: Broadcom BCM63268 pin controller
      8
      9maintainers:
     10  - Álvaro Fernández Rojas <noltari@gmail.com>
     11  - Jonas Gorski <jonas.gorski@gmail.com>
     12
     13description:
     14  Bindings for Broadcom's BCM63268 memory-mapped pin controller.
     15
     16properties:
     17  compatible:
     18    const: brcm,bcm63268-pinctrl
     19
     20  reg:
     21    maxItems: 3
     22
     23patternProperties:
     24  '-pins$':
     25    type: object
     26    $ref: pinmux-node.yaml#
     27
     28    properties:
     29      function:
     30        enum: [ serial_led_clk, serial_led_data, hsspi_cs4, hsspi_cs5,
     31                hsspi_cs6, hsspi_cs7, adsl_spi_miso, adsl_spi_mosi,
     32                vreq_clk, pcie_clkreq_b, robosw_led_clk, robosw_led_data,
     33                nand, gpio35_alt, dectpd, vdsl_phy_override_0,
     34                vdsl_phy_override_1, vdsl_phy_override_2,
     35                vdsl_phy_override_3, dsl_gpio8, dsl_gpio9 ]
     36
     37      pins:
     38        enum: [ gpio0, gpio1, gpio16, gpio17, gpio8, gpio9, gpio18, gpio19,
     39                gpio22, gpio23, gpio30, gpio31, nand_grp, gpio35
     40                dectpd_grp, vdsl_phy_override_0_grp,
     41                vdsl_phy_override_1_grp, vdsl_phy_override_2_grp,
     42                vdsl_phy_override_3_grp, dsl_gpio8, dsl_gpio9 ]
     43
     44allOf:
     45  - $ref: "pinctrl.yaml#"
     46
     47required:
     48  - compatible
     49  - reg
     50
     51additionalProperties: false
     52
     53examples:
     54  - |
     55    pinctrl@10 {
     56      compatible = "brcm,bcm63268-pinctrl";
     57      reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
     58
     59      pinctrl_serial_led: serial_led-pins {
     60        pinctrl_serial_led_clk: serial_led_clk-pins {
     61          function = "serial_led_clk";
     62          pins = "gpio0";
     63        };
     64
     65        pinctrl_serial_led_data: serial_led_data-pins {
     66          function = "serial_led_data";
     67          pins = "gpio1";
     68        };
     69      };
     70
     71      pinctrl_hsspi_cs4: hsspi_cs4-pins {
     72        function = "hsspi_cs4";
     73        pins = "gpio16";
     74      };
     75
     76      pinctrl_hsspi_cs5: hsspi_cs5-pins {
     77        function = "hsspi_cs5";
     78        pins = "gpio17";
     79      };
     80
     81      pinctrl_hsspi_cs6: hsspi_cs6-pins {
     82        function = "hsspi_cs6";
     83        pins = "gpio8";
     84      };
     85
     86      pinctrl_hsspi_cs7: hsspi_cs7-pins {
     87        function = "hsspi_cs7";
     88        pins = "gpio9";
     89      };
     90
     91      pinctrl_adsl_spi: adsl_spi-pins {
     92        pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
     93          function = "adsl_spi_miso";
     94          pins = "gpio18";
     95        };
     96
     97        pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
     98          function = "adsl_spi_mosi";
     99          pins = "gpio19";
    100        };
    101      };
    102
    103      pinctrl_vreq_clk: vreq_clk-pins {
    104        function = "vreq_clk";
    105        pins = "gpio22";
    106      };
    107
    108      pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
    109        function = "pcie_clkreq_b";
    110        pins = "gpio23";
    111      };
    112
    113      pinctrl_robosw_led_clk: robosw_led_clk-pins {
    114        function = "robosw_led_clk";
    115        pins = "gpio30";
    116      };
    117
    118      pinctrl_robosw_led_data: robosw_led_data-pins {
    119        function = "robosw_led_data";
    120        pins = "gpio31";
    121      };
    122
    123      pinctrl_nand: nand-pins {
    124        function = "nand";
    125        group = "nand_grp";
    126      };
    127
    128      pinctrl_gpio35_alt: gpio35_alt-pins {
    129        function = "gpio35_alt";
    130        pin = "gpio35";
    131      };
    132
    133      pinctrl_dectpd: dectpd-pins {
    134        function = "dectpd";
    135        group = "dectpd_grp";
    136      };
    137
    138      pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
    139        function = "vdsl_phy_override_0";
    140        group = "vdsl_phy_override_0_grp";
    141      };
    142
    143      pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
    144        function = "vdsl_phy_override_1";
    145        group = "vdsl_phy_override_1_grp";
    146      };
    147
    148      pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
    149        function = "vdsl_phy_override_2";
    150        group = "vdsl_phy_override_2_grp";
    151      };
    152
    153      pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
    154        function = "vdsl_phy_override_3";
    155        group = "vdsl_phy_override_3_grp";
    156      };
    157
    158      pinctrl_dsl_gpio8: dsl_gpio8-pins {
    159        function = "dsl_gpio8";
    160        group = "dsl_gpio8";
    161      };
    162
    163      pinctrl_dsl_gpio9: dsl_gpio9-pins {
    164        function = "dsl_gpio9";
    165        group = "dsl_gpio9";
    166      };
    167    };