cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
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brcm,ns2-pinmux.txt (3201B)

      1Broadcom Northstar2 IOMUX Controller
      2
      3The Northstar2 IOMUX controller supports group based mux configuration. There
      4are some individual pins that support modifying the pinconf parameters.
      5
      6Required properties:
      7
      8- compatible:
      9    Must be "brcm,ns2-pinmux"
     10
     11- reg:
     12    Define the base and range of the I/O address space that contains the
     13    Northstar2 IOMUX and pin configuration registers.
     14
     15Properties in sub nodes:
     16
     17- function:
     18    The mux function to select
     19
     20- groups:
     21    The list of groups to select with a given function
     22
     23- pins:
     24    List of pin names to change configuration
     25
     26The generic properties bias-disable, bias-pull-down, bias-pull-up,
     27drive-strength, slew-rate, input-enable, input-disable are supported
     28for some individual pins listed at the end.
     29
     30For more details, refer to
     31Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
     32
     33For example:
     34
     35	pinctrl: pinctrl@6501d130 {
     36		compatible = "brcm,ns2-pinmux";
     37		reg = <0x6501d130 0x08>,
     38		      <0x660a0028 0x04>,
     39		      <0x660009b0 0x40>;
     40
     41		pinctrl-names = "default";
     42		pinctrl-0 = <&nand_sel>, <&uart3_rx>, <&sdio0_d4>;
     43
     44		/* Select nand function */
     45		nand_sel: nand_sel {
     46			function = "nand";
     47			groups = "nand_grp";
     48		};
     49
     50		/* Pull up the uart3 rx pin */
     51		uart3_rx: uart3_rx {
     52			pins = "uart3_sin";
     53			bias-pull-up;
     54		};
     55
     56		/* Set the drive strength of sdio d4 pin */
     57		sdio0_d4: sdio0_d4 {
     58			pins = "sdio0_data4";
     59			drive-strength = <8>;
     60		};
     61	};
     62
     63List of supported functions and groups in Northstar2:
     64
     65"nand": "nand_grp"
     66
     67"nor": "nor_data_grp", "nor_adv_grp", "nor_addr_0_3_grp", "nor_addr_4_5_grp",
     68	"nor_addr_6_7_grp", "nor_addr_8_9_grp", "nor_addr_10_11_grp",
     69	"nor_addr_12_15_grp"
     70
     71"gpio": "gpio_0_1_grp", "gpio_2_5_grp", "gpio_6_7_grp", "gpio_8_9_grp",
     72	"gpio_10_11_grp", "gpio_12_13_grp", "gpio_14_17_grp", "gpio_18_19_grp",
     73	"gpio_20_21_grp", "gpio_22_23_grp", "gpio_24_25_grp", "gpio_26_27_grp",
     74	"gpio_28_29_grp", "gpio_30_31_grp"
     75
     76"pcie": "pcie_ab1_clk_wak_grp", "pcie_a3_clk_wak_grp", "pcie_b3_clk_wak_grp",
     77	"pcie_b2_clk_wak_grp", "pcie_a2_clk_wak_grp"
     78
     79"uart0": "uart0_modem_grp", "uart0_rts_cts_grp", "uart0_in_out_grp"
     80
     81"uart1": "uart1_ext_clk_grp", "uart1_dcd_dsr_grp", "uart1_ri_dtr_grp",
     82	"uart1_rts_cts_grp", "uart1_in_out_grp"
     83
     84"uart2": "uart2_rts_cts_grp"
     85
     86"pwm": "pwm_0_grp", "pwm_1_grp", "pwm_2_grp", "pwm_3_grp"
     87
     88
     89List of pins that support pinconf parameters:
     90
     91"qspi_wp", "qspi_hold", "qspi_cs", "qspi_sck", "uart3_sin", "uart3_sout",
     92"qspi_mosi", "qspi_miso", "spi0_fss", "spi0_rxd", "spi0_txd", "spi0_sck",
     93"spi1_fss", "spi1_rxd", "spi1_txd", "spi1_sck", "sdio0_data7",
     94"sdio0_emmc_rst", "sdio0_led_on", "sdio0_wp", "sdio0_data3", "sdio0_data4",
     95"sdio0_data5", "sdio0_data6", "sdio0_cmd", "sdio0_data0", "sdio0_data1",
     96"sdio0_data2", "sdio1_led_on", "sdio1_wp", "sdio0_cd_l", "sdio0_clk",
     97"sdio1_data5", "sdio1_data6", "sdio1_data7", "sdio1_emmc_rst", "sdio1_data1",
     98"sdio1_data2", "sdio1_data3", "sdio1_data4", "sdio1_cd_l", "sdio1_clk",
     99"sdio1_cmd", "sdio1_data0", "ext_mdio_0", "ext_mdc_0", "usb3_p1_vbus_ppc",
    100"usb3_p1_overcurrent", "usb3_p0_vbus_ppc", "usb3_p0_overcurrent",
    101"usb2_presence_indication", "usb2_vbus_present", "usb2_vbus_ppc",
    102"usb2_overcurrent", "sata_led1", "sata_led0"