cachepc-linux

Fork of AMDESE/linux with modifications for CachePC side-channel attack
git clone https://git.sinitax.com/sinitax/cachepc-linux
Log | Files | Refs | README | LICENSE | sfeed.txt

cnxt,cx92755-pinctrl.txt (2930B)


      1Conexant Digicolor CX92755 General Purpose Pin Mapping
      2
      3This document describes the device tree binding of the pin mapping hardware
      4modules in the Conexant Digicolor CX92755 SoCs. The CX92755 in one of the
      5Digicolor series of SoCs.
      6
      7=== Pin Controller Node ===
      8
      9Required Properties:
     10
     11- compatible: Must be "cnxt,cx92755-pinctrl"
     12- reg: Base address of the General Purpose Pin Mapping register block and the
     13  size of the block.
     14- gpio-controller: Marks the device node as a GPIO controller.
     15- #gpio-cells: Must be <2>. The first cell is the pin number and the
     16  second cell is used to specify flags. See include/dt-bindings/gpio/gpio.h
     17  for possible values.
     18
     19For example, the following is the bare minimum node:
     20
     21	pinctrl: pinctrl@f0000e20 {
     22		compatible = "cnxt,cx92755-pinctrl";
     23		reg = <0xf0000e20 0x100>;
     24		gpio-controller;
     25		#gpio-cells = <2>;
     26	};
     27
     28As a pin controller device, in addition to the required properties, this node
     29should also contain the pin configuration nodes that client devices reference,
     30if any.
     31
     32For a general description of GPIO bindings, please refer to ../gpio/gpio.txt.
     33
     34=== Pin Configuration Node ===
     35
     36Each pin configuration node is a sub-node of the pin controller node and is a
     37container of an arbitrary number of subnodes, called pin group nodes in this
     38document.
     39
     40Please refer to the pinctrl-bindings.txt in this directory for details of the
     41common pinctrl bindings used by client devices, including the definition of a
     42"pin configuration node".
     43
     44=== Pin Group Node ===
     45
     46A pin group node specifies the desired pin mux for an arbitrary number of
     47pins. The name of the pin group node is optional and not used.
     48
     49A pin group node only affects the properties specified in the node, and has no
     50effect on any properties that are omitted.
     51
     52The pin group node accepts a subset of the generic pin config properties. For
     53details generic pin config properties, please refer to pinctrl-bindings.txt
     54and <include/linux/pinctrl/pinconfig-generic.h>.
     55
     56Required Pin Group Node Properties:
     57
     58- pins: Multiple strings. Specifies the name(s) of one or more pins to be
     59  configured by this node. The format of a pin name string is "GP_xy", where x
     60  is an uppercase character from 'A' to 'R', and y is a digit from 0 to 7.
     61- function: String. Specifies the pin mux selection. Values must be one of:
     62  "gpio", "client_a", "client_b", "client_c"
     63
     64Example:
     65	pinctrl: pinctrl@f0000e20 {
     66		compatible = "cnxt,cx92755-pinctrl";
     67		reg = <0xf0000e20 0x100>;
     68
     69		uart0_default: uart0_active {
     70			data_signals {
     71				pins = "GP_O0", "GP_O1";
     72				function = "client_b";
     73			};
     74		};
     75	};
     76
     77	uart0: uart@f0000740 {
     78		compatible = "cnxt,cx92755-usart";
     79		...
     80		pinctrl-0 = <&uart0_default>;
     81		pinctrl-names = "default";
     82	};
     83
     84In the example above, a single pin group configuration node defines the
     85"client select" for the Rx and Tx signals of uart0. The uart0 node references
     86that pin configuration node using the &uart0_default phandle.